Does SH3ADD access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
SH3ADD
RISC-V SH3ADD Instruction Details
Instruction ManualR-typeShift left by 3 and add
Instruction Syntax
sh3add rd, rs1, rs2
rd, rs1, rs2: integer registers x0–x31, with no immediate or shift-amount operand.
32-bit R-type: opcode=0110011 (OP), funct7=0010000, funct3=110; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV32/RV64, requiring enabled Zba; use all XLEN bits of rs1, shift left by the fixed 3, then add full-width rs2. Keep the low XLEN bits without word-result sign extension.
Overlapping sources and destination read values before writeback; x0 is always zero and writes to it are discarded. Only registers are computed; memory is not accessed.
ZbaAddress GenerationBit Manipulation
Instruction Behavior
Requires RV32/RV64 Zba. Shift full-width rs1 left by 3, add rs2, and keep the low XLEN bits. Useful for array address generation; no memory access occurs.
SH3ADD Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sh3add
,
,
Execution Context
Assumes Zba is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
t1(x6)
0x00000014
a0(x10)
0x00001000
31..25
24..20
19..15
14..12
11..7
6..0
0010000
funct7
01010
rs2
00110
rs1
110
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x20A362B3
opcode
0110011 -> OP
funct3
110 -> SH3ADD
funct7
0010000 -> SH3ADD selector
rd / rs1 / rs2
t0(x5) / t1(x6)=0x00000014 / a0(x10)=0x00001000
shift and add
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x20A362B3
syntax : sh3add t0(x5), t1(x6), a0(x10)
Result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SH3ADD is a Zba instruction: it shifts rs1 left by 3, adds rs2, and writes the XLEN-wide result to rd.
rs1 is shifted left by 3 and added to rs2, commonly for address generation.
The addition is XLEN-wide; the instruction itself does not access memory.
Common Usage Scenarios
Address & Pointer
RV32/RV64 Zba, x11=3 and x12=0x1000: the example shifts 3 left by 3, adds 0x1000 and writes x10=0x1018; no memory access occurs.
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: integer registers x0–x31, with no immediate or shift-amount operand.
- 32-bit R-type: opcode=0110011 (OP), funct7=0010000, funct3=110; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV32/RV64, requiring enabled Zba; use all XLEN bits of rs1, shift left by the fixed 3, then add full-width rs2. Keep the low XLEN bits without word-result sign extension.
- Overlapping sources and destination read values before writeback; x0 is always zero and writes to it are discarded. Only registers are computed; memory is not accessed.
Pitfalls / Common Confusions
Shift amount is fixed at 3
FAQ
What is the result width of SH3ADD?
This instruction performs the shift and addition at XLEN width and writes the XLEN-wide result to rd.