Does SH3ADD.UW access memory?
No. It operates only on integer registers.
SH3ADD.UW
RISC-V SH3ADD.UW Instruction Details
Instruction ManualR-typeShift unsigned word left by 3 and add (RV64)
Instruction Syntax
sh3add.uw rd, rs1, rs2
rd, rs1 and rs2 select integer registers x0–x31; there is no immediate or shift-amount operand.
32-bit R-type: opcode=0111011 (OP-32), funct7=0010000, funct3=110; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV64 Zba only: zero-extend rs1[31:0], shift left by 3 and add full-width rs2. Keep the low 64 bits without word-result sign extension.
Overlapping operands read values before writeback; x0 is zero and writes to it are discarded. Only integer registers are computed; data memory is not accessed.
ZbaAddress Generation
Instruction Behavior
Zero-extends rs1[31:0], shifts it left by 3, then performs an XLEN-wide addition with rs2. This RV64 Zba instruction can scale an unsigned-word index before adding a base.
SH3ADD.UW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sh3add.uw
,
,
Execution Context
Assumes Zba is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
a6(x16)
0xFFFFFFFFFFFFFFF0
a0(x10)
0x0000000000001000
31..25
24..20
19..15
14..12
11..7
6..0
0010000
funct7
01010
rs2
10000
rs1
110
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x20A862BB
opcode
0111011 -> OP-32
funct3
110 -> SH3ADD.UW
funct7
0010000 -> SH3ADD.UW selector
rd / rs1 / rs2
t0(x5) / a6(x16)[31:0]=0xFFFFFFF0 / a0(x10)=0x0000000000001000
zero-extend, shift, and add
Not computed
x5
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x20A862BB
syntax : sh3add.uw t0(x5), a6(x16), a0(x10)
Result: Not computed
Current architectural state
t0(x5) = 0x0000000000003001; pc = 0x0000000000002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SH3ADD.UW is an RV64 Zba instruction: it zero-extends rs1[31:0], shifts it left by 3, then performs an XLEN-wide add with rs2.
The low 32 bits of rs1 are zero-extended, shifted left by 3, and added to rs2.
The .uw form is an RV64 address-generation instruction; apart from unsigned-word extraction from rs1, the addition is XLEN-wide.
Common Usage Scenarios
Address generation from unsigned word indices
RV64 Zba, x11=3 and x12=0x1000: the example shifts 3 left by 3, adds 0x1000 and writes x10=0x1018; no memory access occurs.
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 select integer registers x0–x31; there is no immediate or shift-amount operand.
- 32-bit R-type: opcode=0111011 (OP-32), funct7=0010000, funct3=110; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV64 Zba only: zero-extend rs1[31:0], shift left by 3 and add full-width rs2. Keep the low 64 bits without word-result sign extension.
- Overlapping operands read values before writeback; x0 is zero and writes to it are discarded. Only integer registers are computed; data memory is not accessed.
Pitfalls / Common Confusions
RV64 only
FAQ
What is the result width of SH3ADD.UW?
The result is the XLEN-wide sum of rs2 and the zero-extended, shifted rs1[31:0], written to rd.