Does SH3ADD.UW access memory?
No. It operates only on integer registers.
SH3ADD.UW
RISC-V SH3ADD.UW Instruction Details
Instruction ManualR-typeShift unsigned word left by 3 and add (RV64)
Instruction Syntax
sh3add.uw rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZbaAddress Generation
Instruction Behavior
Zero-extends rs1[31:0], shifts it left by 3, then performs an XLEN-wide addition with rs2. This RV64 Zba instruction can scale an unsigned-word index before adding a base.
SH3ADD.UW Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
sh3add.uw
,
,
Execution Context
a6(x16)
0xFFFFFFFFFFFFFFF0
a0(x10)
0x0000000000001000
31..25
24..20
19..15
14..12
11..7
6..0
0010000
funct7
01010
rs2
10000
rs1
110
funct3
00101
rd
0111011
opcode
Execution Data Path
instruction
0x20A862BB
opcode
0111011 -> OP-32
funct3
110 -> SH3ADD.UW
funct7
0010000 -> SH3ADD.UW selector
rd / rs1 / rs2
t0(x5) / a6(x16)[31:0]=0xFFFFFFF0 / a0(x10)=0x0000000000001000
zero-extend, shift, and add
EXTZ(0xFFFFFFF0) << 3 = 0x00000007FFFFFF80; 0x0000000000001000 + 0x00000007FFFFFF80 = 0x0000000800000F80
x5
t0(x5) = 0x0000000800000F80
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x20A862BB
syntax : sh3add.uw t0(x5), a6(x16), a0(x10)
result : t0(x5) = 0x0000000800000F80
Architectural Result
t0(x5) = 0x0000000800000F80
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
SH3ADD.UW is an RV64 Zba instruction: it zero-extends rs1[31:0], shifts it left by 3, then performs an XLEN-wide add with rs2.
The low 32 bits of rs1 are zero-extended, shifted left by 3, and added to rs2.
The .uw form is an RV64 address-generation instruction; apart from unsigned-word extraction from rs1, the addition is XLEN-wide.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «sh3add.uw x10, x11, x12 ; x10 = x12 + (zero_ext(x11[31:0]) << 3)».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
RV64 only
FAQ
What is the result width of SH3ADD.UW?
The result is the XLEN-wide sum of rs2 and the zero-extended, shifted rs1[31:0], written to rd.