sext-w

RISC-V sext-w Pseudo-Instruction Details

Assembler pseudo-instruction

RV64 sign-extend-word pseudo-instruction, expanding to addiw rd, rs, 0. It takes the low 32 bits of rs and sign-extends bit 31 to XLEN.

What You Write

sext.w rd, rs

Typical Real Expansion

addiw rd, rs, 0

What This Pseudo Instruction Is Saving You From Writing

RV64 32-bit integer results often need the sign-extension invariant; sext.w names the common addiw +0 use directly.

sext-w primarily means "RV64 32-bit sign extension". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats sext-w as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of ADDIW and the other expanded instructions, not from a separate sext-w hardware opcode.

Availability And Extension Conditions

Base Conditions

RV64I word-instruction semantics

Single-Instruction Or Standard Form

RV64 uses ADDIW rd, rs, 0

Fallback / Boundary

RV32 has no same XLEN-extension need because the register width is already 32 bits.

Notes

The result is sign-extended from bit 31 to XLEN.

How To Read The Expansion

Step 1

ADDIW adds zero, taking the low 32-bit result from rs and sign-extending it to XLEN.

What You May See In objdump / Disassembly

Disassembly may show either the pseudo-instruction or the expanded real instruction, depending on tool options and context.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Normalize a 32-bit signed integer to XLEN on RV64

Read or emit compiler sequences that rely on ADDIW +0

Compare with zext.w to understand 32-bit sign versus zero extension

Pitfalls / Common Confusions

This is sign extension, not zero extension; when bit31 is 1 the high bits become 1

Depends on RV64 ADDIW semantics and has no same meaning on RV32

Use zext.w when 32-bit zero extension is required

FAQ

Is sext-w a real RISC-V instruction?

sext-w is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using sext-w?