sext.w

RISC-V sext.w Pseudo-Instruction Details

Assembler pseudo-instruction

The RISC-V sext.w pseudo-instruction expands to addiw rd, rs, 0. This RV64I form writes the sign extension of rs's low 32 bits to rd.

What You Write

sext.w rd, rs

Typical Real Expansion

addiw rd, rs, 0

What This Pseudo Instruction Is Saving You From Writing

The assembly manual names ADDIW rd, rs, 0 as the sext.w sign-extend-word spelling.

The RISC-V sext.w pseudo-instruction expands to addiw rd, rs, 0; on RV64I it sign-extends rs's low 32-bit result into rd.

Official Semantics Checklist

the RISC-V Assembly Programmer's Manual lists sext.w rd, rs as addiw rd, rs, 0 with the meaning Sign extend word.

Unprivileged ISA Section 4.2.1 says ADDIW rd, rs1, 0 writes the sign extension of rs1's lower 32 bits into rd.

Availability And Extension Conditions

Base Conditions

RV64I ADDIW

Single-Instruction Or Standard Form

sext.w expands to ADDIW rd, rs, 0.

Fallback / Boundary

RV32 does not provide ADDIW.

Notes

The low 32-bit result is sign-extended into rd.

How To Read The Expansion

Step 1

ADDIW rd, rs, 0 sign-extends rs's low 32-bit result into rd.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 29 Table 5

RISC-V Unprivileged ISA Manual 20260120, Section 4.2.1

When To Think Of It First

On RV64I, use sext.w for the table's sign-extend-word operation.

Pitfalls / Common Confusions

sext.w uses the RV64I ADDIW form; do not treat it as an RV32 instruction.

It sign-extends the low 32 bits rather than zero-extending them.

FAQ

Which architecture supports sext.w?

sext.w expands to ADDIW rd, rs, 0, and ADDIW is an RV64I instruction.

Which part does sext.w extend?