zext-h

RISC-V zext-h Pseudo-Instruction Details

Assembler pseudo-instruction

Zero-extend-halfword pseudo-instruction that keeps the low 16 bits and clears the high bits. Without Zbb it can use a shift-left/logical-shift-right sequence; with Zbb it can use a single instruction form.

What You Write

zext.h rd, rs

Typical Real Expansion

# Zbb path zext.h rd, rs # or without Zbb: slli rd, rs, XLEN-16 srli rd, rd, XLEN-16

What This Pseudo Instruction Is Saving You From Writing

Halfword data often needs conversion to an unsigned integer; zext.h explicitly means zero-extend the low 16 bits and lets the toolchain choose an implementation based on Zbb availability.

zext-h primarily means "Zero-extend low 16 bits". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats zext-h as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of ZEXT.H and the other expanded instructions, not from a separate zext-h hardware opcode.

Availability And Extension Conditions

Base Conditions

RV32I/RV64I can express it with a shift sequence

Single-Instruction Or Standard Form

Zbb provides the real ZEXT.H instruction

Fallback / Boundary

Without Zbb, use SLLI followed by SRLI, with shift amounts selected by XLEN.

Notes

Zero-extends the low 16 bits; it is not sign extension.

Toolchain And Linker Boundaries

With Zbb, zext.h can appear as a real single instruction; without Zbb, the assembler can express the same zero-extension intent with SLLI/SRLI.

Disassembly depends on target extensions and tool preference; do not treat the single-instruction path as a base-ISA guarantee.

How To Read The Expansion

Step 1

Zbb path: the real ZEXT.H instruction directly zero-extends the low 16 bits into rd.

Step 2

Without Zbb step 1: SLLI moves the low 16 bits to the top of the register, discarding the original upper bits.

Step 3

Without Zbb step 2: SRLI shifts them back logically, filling upper bits with zeros.

What You May See In objdump / Disassembly

With Zbb, disassembly may show the real zext.h instruction; without Zbb, the shift sequence may still be understood as the pseudo-instruction intent.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Interpret the low 16 bits as an unsigned halfword

Handle UTF-16, halfword arrays, or 16-bit device register values

Express halfword zero-extension intent uniformly on RV32/RV64

Pitfalls / Common Confusions

The available sequence depends on Zbb support

This is zero extension, not sign extension

XLEN in the shift sequence differs on RV32/RV64

FAQ

Is zext-h a real RISC-V instruction?

zext-h is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using zext-h?