zext.h

RISC-V zext.h: Zbb/Zbkb Instruction and Equivalent Shift Sequence

Zbb/Zbkb instruction; equivalent shift sequence

The zext.h instruction zero-extends the low 16 bits to XLEN. It is provided by the Zbb extension and also by the Zbkb extension via RV32 PACK or RV64 PACKW with rs2=x0. The Assembly Manual lists an equivalent SLLI/SRLI shift sequence.

What You Write

zext.h rd, rs

Equivalent Shift Sequence

slli rd, rs, XLEN - 16 srli rd, rd, XLEN - 16

Single Instruction and Equivalent Shift Sequence

The zero extension performed by zext.h has a single-instruction form in Zbb/Zbkb and can also be performed by the Assembly Manual's two-shift sequence. The single instruction has different RV32 and RV64 encodings.

Zbb and Zbkb both provide a single zext.h instruction. Without those single-instruction forms, two shifts can perform the same zero extension of the low 16 bits.

Official Semantics Checklist

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture Section 30.9.50 gives the Zbb zext.h encodings and low-16-bit zero-extension operation.

Sections 30.9.26 and 30.9.28 specify that Zbkb RV32 PACK and RV64 PACKW with rs2=x0 are also zext.h.

The RISC-V Assembly Programmer's Manual lists an equivalent SLLI/SRLI shift sequence.

Availability And Extension Conditions

Base Conditions

The Zbb extension provides zext.h with different RV32 and RV64 encodings.
The Zbkb extension also provides zext.h: PACK with rs2=x0 on RV32, or PACKW with rs2=x0 on RV64.

Single-Instruction Or Standard Form

The target ISA includes the Zbb or Zbkb extension.

Fallback / Boundary

When those single-instruction forms are unavailable, the equivalent SLLI/SRLI shift sequence performs zero extension of the low 16 bits.

Notes

Zero-extends the low 16 bits.

How The Equivalent Shift Sequence Works

Step 1

In the equivalent shift sequence, SLLI shifts the source left by XLEN - 16 bits, inserting zeros into the lower bits.

Step 2

SRLI then shifts right logically with zeros shifted into upper bits, producing the zero-extended low 16 bits.

Official References And Reading Order

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture Section 30.9.50 gives the Zbb zext.h encodings and semantics; Sections 30.9.26 and 30.9.28 specify that Zbkb RV32 PACK and RV64 PACKW with rs2=x0 are also zext.h. RISC-V Assembly Programmer's Manual Table 5 lists an equivalent SLLI/SRLI sequence.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture 20260120, Sections 30.9.26, 30.9.28 and 30.9.50

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 29 Table 5

When To Think Of It First

A single zext.h instruction zero-extends the low 16 bits when the target ISA includes the Zbb or Zbkb extension.

When those single-instruction forms are unavailable, the equivalent SLLI/SRLI shift sequence performs the same zero extension.

Pitfalls / Common Confusions

The absence of Zbb does not imply that zext.h needs two instructions: Zbkb RV32 PACK and RV64 PACKW with rs2=x0 also provide zext.h.

The two-shift sequence performs zero extension, not sign extension.

FAQ

Is zext.h a pseudo-instruction with Zbb?

No. The Unprivileged ISA defines zext.h as a real Zbb instruction and gives RV32 and RV64 encodings.

Is a two-shift sequence required without Zbb?

No. Zbkb RV32 PACK and RV64 PACKW with rs2=x0 are also zext.h. Check whether the target ISA provides a single-instruction form.

What is the equivalent shift sequence?

The RISC-V Assembly Programmer's Manual lists slli rd, rs, XLEN - 16 followed by srli rd, rd, XLEN - 16 to zero-extend the source's low 16 bits to XLEN.