Does ZEXT.H access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
ZEXT.H
RISC-V ZEXT.H Instruction Details
Instruction ManualR-typeZero-extend halfword
Instruction Syntax
zext.h rd, rs
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZbbBit ManipulationInteger Operation
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
ZEXT-H uses opcode 0110011 (0x33) in RV32 and opcode 0111011 (0x3b) in RV64, funct3 100, funct7 0000100, rs2 0. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: RV32 0110011 (0x33); RV64 0111011 (0x3b)
funct3: 100 (0x4)
funct7: 0000100 (0x04)
rs2: 0
Instruction Behavior
Zero-extends the least-significant 16 bits of rs to XLEN. It is a Zbb instruction with different encodings in RV32 and RV64.
ZEXT.H Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs
zext.h
,
Execution Context
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0000100
funct7
00000
rs2
00110
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x080342B3
opcode
0110011 -> OP
funct3
100 -> ZEXT.H
funct7 / rs2
0000100 / 00000 -> ZEXT.H selector
rd / rs
t0(x5) / t1(x6)=0x00000014
16-bit zero extension
0x0014; insert 0 into bits 31:16 -> 0x00000014
x5
t0(x5) = 0x00000014
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x080342B3
syntax : zext.h t0(x5), t1(x6)
result : t0(x5) = 0x00000014
Architectural Result
t0(x5) = 0x00000014
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
ZEXT.H is a Zbb instruction: it reads rs[15:0] and zero-extends that value to XLEN. RV32 and RV64 use different encodings.
Only the low 16 bits of rs1 are read and zero-extended to XLEN.
It differs from SEXT.H; bit 15 is not propagated into upper bits.
Common Usage Scenarios
Bit Manipulation
Understand this scenario with real code like «zext.h x10, x11 ; x10 = zero_ext(x11[15:0])».
Type Conversion
Understand this scenario with real code like «zext.h x10, x11 ; x10 = zero_ext(x11[15:0])».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
Only rs[15:0] is used; bit 15 is not propagated into higher bits.
RV32 uses OP encoding and RV64 uses OP-32 encoding.
FAQ
What is the result width of ZEXT.H?
The result is written to rd at the current XLEN: 32 bits in RV32 and 64 bits in RV64; in both cases every bit above bit 15 is zero.