Does ZEXT.H access memory?
No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.
ZEXT.H
RISC-V ZEXT.H Instruction Details
Instruction ManualR-typeZero-extend halfword
Instruction Syntax
zext.h rd, rs1
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbBit ManipulationInteger Operation
Instruction Behavior
Zero-extends the least-significant 16 bits of rs to XLEN. Replaces slli+srai (sign-ext) or slli+srli (zero-ext) sequences. Part of Zbb.
Quick Understanding & Search Notes
ZEXT.H is a B/Zbb instruction for zero-extend low halfword. This page is checked against the official B extension semantics, with emphasis on XLEN, W suffixes, .uw suffixes, and bitwise or rotate boundaries.
Only the low 16 bits of rs1 are read and zero-extended to XLEN.
It differs from SEXT.H; bit 15 is not propagated into upper bits.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «zext.h x10, x11 ; x10 = zero_ext(x11[15:0])».
Type Conversion
Understand this scenario with real code like «zext.h x10, x11 ; x10 = zero_ext(x11[15:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Only extends lower 16 bits
FAQ
What is the result width of ZEXT.H?
Except that W-suffixed forms produce a 32-bit result then sign-extend and .uw forms first extract a 32-bit unsigned operand, the result is written to rd at XLEN width.