Does ZEXT.H access memory?
No. It reads an integer source register and writes an integer destination register, with no data-memory access.
ZEXT.H
RISC-V ZEXT.H Instruction Details
Instruction ManualR-typeZero-extend halfword
Instruction Syntax
zext.h rd, rs
rd and rs select x0–x31. There is one integer source and no immediate; the encoded rs2 field is fixed to 00000.
funct7=0000100 and funct3=100; RV32 uses opcode=0110011 and RV64 uses opcode=0111011.
Read pre-execution rs[15:0], fill all bits above bit15 with zero and write the XLEN-wide result to rd; rd=x0 discards writeback.
Available with Zbb or Zbkb on RV32/RV64. Zbkb RV32 PACK / RV64 PACKW with rs2=x0 is this instruction.
No data-memory access; rd=rs is legal and reads the source before writeback.
ZbbZbkbBit ManipulationInteger Operation
Instruction Behavior
Zero-extends rs[15:0] to XLEN. Zbb and Zbkb both provide this instruction: RV32 uses PACK with rs2=x0, while RV64 uses PACKW with rs2=x0.
ZEXT.H Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs
zext.h
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0000100
funct7
00000
rs2
00110
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x080342B3
opcode
0110011 -> OP
funct3
100 -> ZEXT.H
funct7 / rs2
0000100 / 00000 -> ZEXT.H selector
rd / rs
t0(x5) / t1(x6)=0x00000014
16-bit zero extension
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x080342B3
syntax : zext.h t0(x5), t1(x6)
Result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Zero-extends rs[15:0] to XLEN. Zbb and Zbkb both provide this instruction: RV32 uses PACK with rs2=x0, while RV64 uses PACKW with rs2=x0.
Only the low 16 bits of rs1 are read and zero-extended to XLEN.
It differs from SEXT.H; bit 15 is not propagated into upper bits.
Zbb or Zbkb provides the single instruction. RV32 uses opcode=0110011 and RV64 uses opcode=0111011, with funct7=0000100, rs2=00000 and funct3=100.
Common Usage Scenarios
Zero-extend low 16 bits
RV32/RV64 Zbb or Zbkb, x11=0x12348001: zext.h x10, x11 produces x10=0x8001 with zero upper bits.
Pre-Use Checklist
Syntax Check
- rd and rs select x0–x31. There is one integer source and no immediate; the encoded rs2 field is fixed to 00000.
- funct7=0000100 and funct3=100; RV32 uses opcode=0110011 and RV64 uses opcode=0111011.
Semantic Check
- Read pre-execution rs[15:0], fill all bits above bit15 with zero and write the XLEN-wide result to rd; rd=x0 discards writeback.
- Available with Zbb or Zbkb on RV32/RV64. Zbkb RV32 PACK / RV64 PACKW with rs2=x0 is this instruction.
- No data-memory access; rd=rs is legal and reads the source before writeback.
Pitfalls / Common Confusions
Only rs[15:0] is used; bit 15 is not propagated into higher bits.
RV32 uses OP encoding and RV64 uses OP-32 encoding.
FAQ
What is the result width of ZEXT.H?
The result is written to rd at the current XLEN: 32 bits in RV32 and 64 bits in RV64; in both cases every bit above bit 15 is zero.