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SEXT.H

RISC-V SEXT.H Instruction Details

Instruction ManualI-type

Sign-extend halfword

Instruction Syntax

sext.h rd, rs
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
BZbbBit ManipulationInteger Operation
Related Search Terms
sext.h instructionRISC-V sext.hsext.h syntaxsext.h encodingsign-extend low halfwordsext.h Zbb

Instruction Behavior

Sign-extends the least-significant 16 bits of rs to XLEN by copying bit 15 to every higher bit. Part of Zbb.

SEXT.H Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
rs
sext.h
,
Execution Context
t1(x6)
0x00000014
31..20
19..15
14..12
11..7
6..0
011000000101
fixed imm[11:0]
00110
rs1
001
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x60531293
opcode
0010011 -> OP-IMM
funct3
001 -> SEXT.H
fixed imm[11:0]
011000000101 -> SEXT.H selector
rd / rs
t0(x5) / t1(x6)=0x00000014
fixed imm[11:0]
011000000101 -> SEXT.H selector (not an arithmetic immediate)
16-bit sign extension
0x0014; copy bit 15 to bits 31:16 -> 0x00000014
x5
t0(x5) = 0x00000014
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x60531293
syntax : sext.h t0(x5), t1(x6)
result : t0(x5) = 0x00000014
Architectural Result
t0(x5) = 0x00000014

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

SEXT.H reads only rs[15:0], copies bit 15 to all higher bits, and writes the XLEN-wide result to rd.

Only the low 16 bits are read and bit 15 is sign-extended.
It differs from ZEXT.H; upper bits are filled from the sign bit.
RISC-V Unprivileged ISA Manual: B bit-manipulation extension

Common Usage Scenarios

Type Conversion

Understand this scenario with real code like «sext.h x10, x11 ; x10 = sign_ext(x11[15:0])».

Pre-Use Checklist

Syntax Check
  • Verify the immediate field is within the valid range.
  • Confirm source register rs1 points to the correct operand.
Semantic Check
  • Check if the immediate sign-extension matches expectations.
  • Ensure the result register rd has a clear purpose.

Pitfalls / Common Confusions

Only extends lower 16 bits

FAQ

Does SEXT.H access memory?

No. It only reads and writes integer registers; any memory access must be performed by a separate load or store instruction.

What is the result width of SEXT.H?

SEXT.H uses bit 15 for every upper rd bit: bit 15=0 fills them with zero, and bit 15=1 fills them with one.