RISC-V BCLR Instruction Details
Instruction ManualR-typeClear single bit by register index
Instruction Syntax
rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
The low 5 (RV32) or 6 (RV64) rs2 bits select the index; other bits are ignored.
Requires Zbs on RV32/RV64; clear the selected bit and preserve the other rs1 bits.
Instruction Behavior
Zbs bclr clears one rs1 bit selected by the low log2(XLEN) bits of rs2 and writes rd.
BCLR Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Zbs bclr clears one rs1 bit selected by the low log2(XLEN) bits of rs2 and writes rd.
Common Usage Scenarios
RV32/RV64 Zbs, x11=0xff and x12=35: RV32 selects index 3 and writes x10=0xf7; RV64 selects index 35 and writes x10=0xff.
RV32/RV64 Zbs, x11=0xff and x12=35: RV32 selects index 3 and writes x10=0xf7; RV64 selects index 35 and writes x10=0xff.
RV32/RV64 Zbs, x11=0xff and x12=35: RV32 selects index 3 and writes x10=0xf7; RV64 selects index 35 and writes x10=0xff.
Pre-Use Checklist
- rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
- The low 5 (RV32) or 6 (RV64) rs2 bits select the index; other bits are ignored.
- Requires Zbs on RV32/RV64; clear the selected bit and preserve the other rs1 bits.