RISC-V BEXT Instruction Details
Instruction ManualR-typeExtract single bit by register index
Instruction Syntax
rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
The low 5 (RV32) or 6 (RV64) rs2 bits select the index; other bits are ignored.
Requires Zbs on RV32/RV64; the result is 0 or 1, without preserving the bit position.
Instruction Behavior
Zbs bext extracts one rs1 bit selected by the low log2(XLEN) bits of rs2; rd is 0 or 1.
BEXT Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Zbs bext extracts one rs1 bit selected by the low log2(XLEN) bits of rs2; rd is 0 or 1.
Common Usage Scenarios
RV32/RV64 Zbs, x11=0xff and x12=35: RV32 extracts bit 3 to x10=1; RV64 extracts bit 35 to x10=0.
RV32/RV64 Zbs, x11=0xff and x12=35: RV32 extracts bit 3 to x10=1; RV64 extracts bit 35 to x10=0.
RV32/RV64 Zbs, x11=0xff and x12=35: RV32 extracts bit 3 to x10=1; RV64 extracts bit 35 to x10=0.
Pre-Use Checklist
- rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
- The low 5 (RV32) or 6 (RV64) rs2 bits select the index; other bits are ignored.
- Requires Zbs on RV32/RV64; the result is 0 or 1, without preserving the bit position.