Does binv access memory?
No. It reads integer register operands and writes rd only.
BINV
RISC-V BINV Instruction Details
Instruction ManualR-typeInvert single bit by register index
Instruction Syntax
binv rd, rs1, rs2
Operand Breakdown
Destination rd: receives the result after changing or extracting the selected single bit; a write to rd=x0 is discarded.
Source rs1: supplies the XLEN-bit value whose bit is changed or extracted.
Index register rs2: only its low log2(XLEN) bits select the bit position; its remaining bits do not contribute to the index.
ZbsBit ManipulationSingle-Bit Operation
Related Search Terms
Instruction Behavior
binv is a Zbs single-bit invert instruction. The bit index comes from the low log2(XLEN) bits of rs2.
BINV Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
binv
,
,
Execution Context
a0(x10)
0x00001000
31..25
24..20
19..15
14..12
11..7
6..0
0110100
funct7
10000
rs2
01010
rs1
001
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x690512B3
opcode
0110011 -> OP
funct3
001 -> BINV
funct7
0110100 -> single-bit operation selector
rd / rs1 / rs2
t0(x5) / a0(x10)=0x00001000 / a6(x16)=0xFFFFFFF0
rs2[4:0]
0xFFFFFFF0 & 31 -> index=16
single-bit invert
0x00001000 ^ 0x00010000 = 0x00011000
x5
t0(x5) = 0x00011000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x690512B3
syntax : binv t0(x5), a0(x10), a6(x16)
result : t0(x5) = 0x00011000
Architectural Result
t0(x5) = 0x00011000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
binv is a Zbs single-bit invert instruction. The bit index comes from the low log2(XLEN) bits of rs2.
These instructions are part of a B-extension subset and operate on XLEN-wide integer register values.
The register-index form uses only the low log2(XLEN) bits of rs2 to select the bit.
binv changes one selected bit and leaves the other bits from rs1 unchanged.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «binv x10, x11, x12 ; x10 = x11 ^ (1 << (x12 & (XLEN-1)))».
Immediates & Constants
Understand this scenario with real code like «binv x10, x11, x12 ; x10 = x11 ^ (1 << (x12 & (XLEN-1)))».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
The register-index form uses only the low log2(XLEN) bits of rs2 to select the bit.
binv changes one selected bit and leaves the other bits from rs1 unchanged.
FAQ
How is the bit index selected for binv?
The low log2(XLEN) bits of rs2 select the bit, so higher bits do not extend the index range.