BSET

RISC-V BSET Instruction Details

Instruction ManualR-type

Set single bit by register index

Instruction Syntax

bset rd, rs1, rs2

rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.

rs2 selects the index register; use only its low 5 bits on RV32 or low 6 bits on RV64 and ignore the rest.

Requires Zbs 1.0 on RV32/RV64; set the selected bit to 1 and preserve the other rs1 bits; an already-set bit stays 1.

ZbsBit ManipulationSingle-Bit Operation

Instruction Behavior

bset is a Zbs single-bit set instruction. The bit index comes from the low log2(XLEN) bits of rs2.

BSET Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
rs1
rs2
bset
,
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

a0(x10)
0x00001000
a6(x16)
0xFFFFFFF0
31..25
24..20
19..15
14..12
11..7
6..0
0010100
funct7
10000
rs2
01010
rs1
001
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x290512B3
opcode
0110011 -> OP
funct3
001 -> BSET
funct7
0010100 -> single-bit operation selector
rd / rs1 / rs2
t0(x5) / a0(x10)=0x00001000 / a6(x16)=0xFFFFFFF0
rs2[4:0]
0xFFFFFFF0 & 31 -> index=16
single-bit set
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x290512B3
syntax : bset t0(x5), a0(x10), a6(x16)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

bset is a Zbs single-bit set instruction. The bit index comes from the low log2(XLEN) bits of rs2.

This instruction belongs to Zbs 1.0 on RV32 and RV64 and operates on XLEN-bit integer register values.
The register-index form uses only the low log2(XLEN) bits of rs2 to select the bit.
bset sets the selected bit to 1 and leaves the other rs1 bits unchanged; an already-set bit stays 1.

Common Usage Scenarios

Bit Operations & Masks

RV32/RV64 Zbs, x11=0 and x12=35: RV32 selects index 3 and writes x10=0x8; RV64 selects index 35 and writes x10=0x800000000.

Pre-Use Checklist

Syntax Check
  • rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
  • rs2 selects the index register; use only its low 5 bits on RV32 or low 6 bits on RV64 and ignore the rest.
Semantic Check
  • Requires Zbs 1.0 on RV32/RV64; set the selected bit to 1 and preserve the other rs1 bits; an already-set bit stays 1.

Pitfalls / Common Confusions

The register-index form uses only the low log2(XLEN) bits of rs2 to select the bit.
bset sets the selected bit to 1 and leaves the other rs1 bits unchanged; an already-set bit stays 1.

FAQ

Does bset access memory?

No data-memory access occurs. The data operation reads integer registers and writes rd; a result directed to x0 is discarded.

How is the bit index selected for bset?

The low log2(XLEN) bits of rs2 select the bit, so higher bits do not extend the index range.