RVOPcode
Home/Instructions/Bit Clear Immediate
BCLRI

RISC-V BCLRI Instruction Details

Instruction ManualOP-IMM (I-type)

Clear single bit by immediate index

Instruction Syntax

bclri rd, rs1, shamt

rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.

shamt is a bit index: 0–31 on RV32 or 0–63 on RV64; RV32 encodings with shamt[5]=1 are reserved.

Requires Zbs on RV32/RV64; clear the selected bit and preserve the other rs1 bits.

BZbsBit ManipulationSingle-Bit Operation
Related Search Terms
bclri instructionbclri syntaxZbs bclriclear bit immediatebclri bitmanip

Instruction Behavior

Zbs bclri clears one bit indexed by shamt: 0–31 on RV32 or 0–63 on RV64. RV32 encodings with shamt[5]=1 are reserved.

BCLRI Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
rs1
shamt
bclri
,
,
Execution Context

This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.

a0(x10)
0x00001000
31..25
24..20
19..15
14..12
11..7
6..0
0100100
fixed imm[11:5]
01100
shamt[4:0]
01010
rs1
001
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x48C51293
opcode
0010011 -> OP-IMM
funct3
001 -> BCLRI
imm[11:5]
imm[11:5]=0100100 fixed
rd / rs1
t0(x5) / a0(x10)=0x00001000
imm[11:5] + shamt[4:0]
imm[11:5]=0100100 fixed -> index=12
single-bit clear
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x48C51293
syntax : bclri t0(x5), a0(x10), 12
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

bclri uses shamt to select and clear one bit; RV32 encodings with shamt[5]=1 are reserved.

bclri belongs to Zbs and operates on XLEN-wide integer-register bit patterns.
The index uses the low log2(XLEN) bits of shamt; RV32 encodings with shamt[5]=1 are reserved.
bclri changes one selected bit and leaves the other bits from rs1 unchanged.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture

Common Usage Scenarios

Bit Operations & Masks

RV32/RV64 Zbs, x11=0xff and shamt=3: clear bit 3, giving x10=0xf7; other bits are unchanged.

Pre-Use Checklist

Syntax Check
  • rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
  • shamt is a bit index: 0–31 on RV32 or 0–63 on RV64; RV32 encodings with shamt[5]=1 are reserved.
Semantic Check
  • Requires Zbs on RV32/RV64; clear the selected bit and preserve the other rs1 bits.

Pitfalls / Common Confusions

The index uses the low log2(XLEN) bits of shamt. RV32 encodings with shamt[5]=1 are reserved, so RV32 encodes 0..31 and RV64 encodes 0..63.
bclri changes one selected bit and leaves the other bits from rs1 unchanged.