Does bclri access memory?
No. It reads integer register operands and writes rd only.
BCLRI
RISC-V BCLRI Instruction Details
Instruction ManualOP-IMM (I-type)Clear single bit by immediate index
Instruction Syntax
bclri rd, rs1, shamt
Operand Breakdown
This is a OP-IMM (I-type)-format instruction. Confirm operand positions based on the assembly syntax.
BZbsBit ManipulationSingle-Bit Operation
Related Search Terms
Instruction Behavior
bclri is a Zbs single-bit clear instruction. The bit index comes from shamt; RV32 encodings with shamt[5]=1 are reserved.
BCLRI Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
shamt
bclri
,
,
Execution Context
a0(x10)
0x00001000
31..25
24..20
19..15
14..12
11..7
6..0
0100100
fixed imm[11:5]
01100
shamt[4:0]
01010
rs1
001
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x48C51293
opcode
0010011 -> OP-IMM
funct3
001 -> BCLRI
imm[11:5]
imm[11:5]=0100100 fixed
rd / rs1
t0(x5) / a0(x10)=0x00001000
imm[11:5] + shamt[4:0]
imm[11:5]=0100100 fixed -> index=12
single-bit clear
0x00001000 & ~(0x00001000) = 0x00000000
x5
t0(x5) = 0x00000000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x48C51293
syntax : bclri t0(x5), a0(x10), 12
result : t0(x5) = 0x00000000
Architectural Result
t0(x5) = 0x00000000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
bclri uses shamt to select and clear one bit; RV32 encodings with shamt[5]=1 are reserved.
bclri belongs to Zbs and operates on XLEN-wide integer-register bit patterns.
The index uses the low log2(XLEN) bits of shamt; RV32 encodings with shamt[5]=1 are reserved.
bclri changes one selected bit and leaves the other bits from rs1 unchanged.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «bclri x10, x11, 3 ; x10 = x11 & ~(1 << 3)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OP-IMM (I-type).
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The index uses the low log2(XLEN) bits of shamt. RV32 encodings with shamt[5]=1 are reserved, so RV32 encodes 0..31 and RV64 encodes 0..63.
bclri changes one selected bit and leaves the other bits from rs1 unchanged.
FAQ
How is the bit index selected for bclri?
The low log2(XLEN) bits of shamt select the bit. RV32 encodings with shamt[5]=1 are reserved, so RV32 encodes 0..31 and RV64 encodes 0..63.