Does andn access memory?
No. It reads integer register operands and writes rd only.
ANDN
RISC-V ANDN Instruction Details
Instruction ManualR-typeAND with inverted operand: rd = rs1 & ~rs2
Instruction Syntax
andn rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
BZbbZbkbBit ManipulationInteger Operation
Related Search Terms
Instruction Behavior
andn computes rs1 & ~rs2: it inverts rs2 bit by bit, then ANDs it with rs1.
ANDN Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
andn
,
,
Execution Context
a0(x10)
0x00001000
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0100000
funct7
00110
rs2
01010
rs1
111
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x406572B3
opcode
0110011 -> OP
funct3
111 -> ANDN
funct7
0100000 -> ANDN selector
rd / rs1 / rs2
t0(x5) / a0(x10) / t1(x6)
bitwise ALU
0x00001000 & ~0x00000014 = 0x00001000
x5
t0(x5) = 0x00001000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x406572B3
syntax : andn t0(x5), a0(x10), t1(x6)
result : t0(x5) = 0x00001000
Architectural Result
t0(x5) = 0x00001000
Bit-by-Bit Logic View
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1
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0
rs1
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0
1
0
1
1
rs2 (inverted)
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
& ~
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
andn computes rs1 & ~rs2: it inverts rs2 bit by bit, then ANDs it with rs1.
andn belongs to Zbb and is also included in Zbkb. It operates on XLEN-wide integer-register bit patterns.
rs2 is inverted before ANDing with rs1; do not read it as ~rs1 & rs2.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «andn x10, x11, x12 ; x10 = x11 & ~x12».
Register Operations
Understand this scenario with real code like «andn x10, x11, x12 ; x10 = x11 & ~x12».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
rs2 is inverted before ANDing with rs1; do not read it as ~rs1 & rs2.
FAQ
Does andn interpret signed numbers?
These bit operations work on bit patterns directly; aside from the specified word-width selection, arithmetic signed magnitude is not used.