RISC-V ANDN Instruction Details
Instruction ManualR-typeAND with inverted operand: rd = rs1 & ~rs2
Instruction Syntax
rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
rs2 is the second source, inverted across XLEN bits; rs1 is not inverted.
Requires Zbb or Zbkb on RV32/RV64; rd = rs1 & ~rs2.
Instruction Behavior
With Zbb or Zbkb, andn computes rd = rs1 & ~rs2 across XLEN bits.
ANDN Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
andn computes rs1 & ~rs2: it inverts rs2 bit by bit, then ANDs it with rs1.
Common Usage Scenarios
RV32/RV64 with Zbb or Zbkb; x11=0xff and x12=0x0f: x10=0xf0, clearing bits selected by the mask.
RV32/RV64 with Zbb or Zbkb; x11=0xff and x12=0x0f: x10=0xf0, clearing bits selected by the mask.
Pre-Use Checklist
- rd and rs1 select x0–x31; sources are read before writeback, and x0 writes are discarded.
- rs2 is the second source, inverted across XLEN bits; rs1 is not inverted.
- Requires Zbb or Zbkb on RV32/RV64; rd = rs1 & ~rs2.