Does ORN access memory?
No. This instruction reads its integer source registers and writes the computed result to rd; it performs no data-memory load or store.
ORN
RISC-V ORN Instruction Details
Instruction ManualR-typeOR with inverted operand: rd = rs1 | ~rs2
Instruction Syntax
orn rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: integer registers x0–x31; no immediate or rs3 operand.
32-bit OP: opcode=0110011, funct7=0100000, funct3=110; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV32/RV64; requires enabled Zbb or Zbkb; B includes Zbb.
Compute rs1 | ~rs2 bit by bit; inversion covers all XLEN bits.
x0 is always zero and discards writes; rd may overlap a source, using source values before writeback. Only integer registers are operated on, with no data-memory access.
BZbbZbkbBit ManipulationInteger Operation
Related Search Terms
Instruction Behavior
Bitwise OR of rs1 with the bitwise inversion of rs2: rd = rs1 | ~rs2. Part of Zbb and Zbkb.
ORN Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
orn
,
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
a0(x10)
0x00001000
t1(x6)
0x00000014
31..25
24..20
19..15
14..12
11..7
6..0
0100000
funct7
00110
rs2
01010
rs1
110
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x406562B3
opcode
0110011 -> OP
funct3
110 -> ORN
funct7
0100000 -> ORN selector
rd / rs1 / rs2
t0(x5) / a0(x10) / t1(x6)
bitwise ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x406562B3
syntax : orn t0(x5), a0(x10), t1(x6)
Pending result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
Bit-by-Bit Logic View
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rs1
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rs2 (inverted)
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This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
Invert all XLEN bits of rs2, OR them with rs1, and write rd. Available in RV32/RV64 with Zbb or Zbkb.
The second source rs2 is inverted; rs1 is not.
The result is an XLEN-wide bitwise value, not a comparison or conditional branch.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «orn x10, x11, x12 ; x10 = x11 | ~x12».
Crypto & Security
Understand this scenario with real code like «orn x10, x11, x12 ; x10 = x11 | ~x12».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: integer registers x0–x31; no immediate or rs3 operand.
- 32-bit OP: opcode=0110011, funct7=0100000, funct3=110; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV32/RV64; requires enabled Zbb or Zbkb; B includes Zbb.
- Compute rs1 | ~rs2 bit by bit; inversion covers all XLEN bits.
- x0 is always zero and discards writes; rd may overlap a source, using source values before writeback. Only integer registers are operated on, with no data-memory access.
Pitfalls / Common Confusions
Note distinction from regular OR: second operand is inverted first
FAQ
What is the result width of ORN?
ORN computes rs1 | ~rs2 bit by bit across the complete XLEN-wide value and writes an equally wide result to rd.