Does XNOR access memory?
No. It operates only on integer registers.
XNOR
RISC-V XNOR Instruction Details
Instruction ManualR-typeExclusive NOR: rd = ~(rs1 ^ rs2)
Instruction Syntax
xnor rd, rs1, rs2
rd, rs1 and rs2 select integer registers x0–x31; there is no immediate operand.
32-bit R-type OP: opcode=0110011, funct7=0100000, funct3=100; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
RV32/RV64, requiring Zbb or Zbkb: compute ~(rs1 ^ rs2) across XLEN bits. Equal bits produce 1 and different bits produce 0, rather than one Boolean equality result.
Overlapping operands read old values; x0 supplies zero and writes to it are discarded. No data-memory access occurs.
ZbbZbkbBit ManipulationInteger Operation
Instruction Behavior
Bitwise exclusive-NOR: rd = ~(rs1 ^ rs2). Part of Zbb and Zbkb.
XNOR Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
xnor
,
,
Execution Context
Assumes Zbb or Zbkb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.
t1(x6)
0x00000014
t2(x7)
0x00000007
31..25
24..20
19..15
14..12
11..7
6..0
0100000
funct7
00111
rs2
00110
rs1
100
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x407342B3
opcode
0110011 -> OP
funct3
100 -> XNOR
funct7
0100000 -> XNOR selector
rd / rs1 / rs2
t0(x5) / t1(x6) / t2(x7)
bitwise ALU
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x407342B3
syntax : xnor t0(x5), t1(x6), t2(x7)
Result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
XNOR inverts the XOR of each rs1/rs2 bit and writes the XLEN-wide result to rd. It is listed in both Zbb and Zbkb.
XNOR means ~(rs1 ^ rs2), not NOR.
Bits are computed independently: equal bits produce 1 and different bits produce 0.
Common Usage Scenarios
Bitwise equality masks
RV32/RV64 with Zbb or Zbkb, x11=0xf0 and x12=0x0f: XNOR writes x10=0xffffff00 (RV32) or 0xffffffffffffff00 (RV64).
Inverting an XOR result
RV32/RV64 with Zbb or Zbkb, x11=0xf0 and x12=0x0f: XNOR writes x10=0xffffff00 (RV32) or 0xffffffffffffff00 (RV64).
Pre-Use Checklist
Syntax Check
- rd, rs1 and rs2 select integer registers x0–x31; there is no immediate operand.
- 32-bit R-type OP: opcode=0110011, funct7=0100000, funct3=100; rs2, rs1 and rd occupy bits24:20, 19:15 and 11:7.
Semantic Check
- RV32/RV64, requiring Zbb or Zbkb: compute ~(rs1 ^ rs2) across XLEN bits. Equal bits produce 1 and different bits produce 0, rather than one Boolean equality result.
- Overlapping operands read old values; x0 supplies zero and writes to it are discarded. No data-memory access occurs.
Pitfalls / Common Confusions
XNOR is not NOR
The result is a per-bit equality mask; only an all-one rd means the XLEN-bit patterns are wholly equal
FAQ
What is the result width of XNOR?
XNOR writes the XLEN-wide ~(rs1 ^ rs2) result to rd; each output bit depends only on its corresponding two input bits.