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SEXT.B

RISC-V SEXT.B Instruction Details

Instruction ManualI-type

Sign-extend byte

Instruction Syntax

sext.b rd, rs
Operand Breakdown
rd, rs: integer registers x0–x31; no immediate operand.
32-bit OP-IMM: opcode=0010011, funct3=001, fixed imm[11:0]=011000000100; this is an operation selector, not an immediate operand.
RV32/RV64; requires enabled Zbb; B includes Zbb.
Take the low 8 source bits and copy bit7 into all higher bits for an XLEN-wide result.
x0 is always zero and discards writes; rd may overlap a source, using values before writeback. Only integer registers are operated on, with no data-memory access.
BZbbBit ManipulationInteger Operation
Related Search Terms
sext.b instructionRISC-V sext.bsext.b syntaxsext.b encodingsign-extend low bytesext.b Zbb

Instruction Behavior

Sign-extends the least-significant 8 bits of rs to XLEN by copying bit 7 to every higher bit. Part of Zbb.

SEXT.B Decode And Execute Animation

Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.

rd
rs
sext.b
,
Execution Context

Assumes Zbb is enabled at the selected XLEN, with the fixed register values below and PC=0x2000; fetch succeeds and no asynchronous interrupt occurs. Steps are a teaching decomposition.

t1(x6)
0x00000014
31..20
19..15
14..12
11..7
6..0
011000000100
fixed imm[11:0]
00110
rs1
001
funct3
00101
rd
0010011
opcode
Execution Data Path
instruction
0x60431293
opcode
0010011 -> OP-IMM
funct3
001 -> SEXT.B
fixed imm[11:0]
011000000100 -> SEXT.B selector
rd / rs
t0(x5) / t1(x6)=0x00000014
fixed imm[11:0]
011000000100 -> SEXT.B selector (not an arithmetic immediate)
8-bit sign extension
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step

Concept Step: receive the 32-bit instruction encoding

The machine code is split by the current instruction format; the animation starts from encoding/decode.

encoding: 0x60431293
syntax : sext.b t0(x5), t1(x6)
Result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000

This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.

Quick Understanding & Search Notes

SEXT.B reads only rs[7:0], copies bit 7 to all higher bits, and writes the XLEN-wide result to rd.

Only the low 8 bits are read and bit 7 is sign-extended.
This is sign extension: bit 7=1 fills upper bits with ones; bit 7=0 fills them with zeros.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, §30.9.37

Common Usage Scenarios

Sign extension

RV32 Zbb, x11=0x12345680: sext.b x10, x11 writes x10=0xFFFFFF80 (-128); RV64 writes 0xFFFFFFFFFFFFFF80.

Pre-Use Checklist

Syntax Check
  • rd, rs: integer registers x0–x31; no immediate operand.
  • 32-bit OP-IMM: opcode=0010011, funct3=001, fixed imm[11:0]=011000000100; this is an operation selector, not an immediate operand.
Semantic Check
  • RV32/RV64; requires enabled Zbb; B includes Zbb.
  • Take the low 8 source bits and copy bit7 into all higher bits for an XLEN-wide result.
  • x0 is always zero and discards writes; rd may overlap a source, using values before writeback. Only integer registers are operated on, with no data-memory access.

Pitfalls / Common Confusions

Only extends lower 8 bits

FAQ

Does SEXT.B access memory?

It does not access data memory; it reads integer source registers and writes the computed result to rd.

What is the result width of SEXT.B?

SEXT.B uses bit 7 for every upper rd bit: bit 7=0 fills them with zero, and bit 7=1 fills them with one.