zext.b
RISC-V zext.b Pseudo-Instruction Details
Assembler pseudo-instructionThe RISC-V zext.b pseudo-instruction expands to andi rd, rs, 255. ANDI bitwise-ANDs rs with a sign-extended 12-bit immediate; 255 retains the low 8 bits.
What You Write
zext.b rd, rs
Typical Real Expansion
andi rd, rs, 255
What This Pseudo Instruction Is Saving You From Writing
The assembly manual names ANDI rd, rs, 255 as the zext.b zero-extend-byte spelling.
The RISC-V zext.b pseudo-instruction expands to andi rd, rs, 255; that immediate mask retains rs's low 8 bits.
Official Semantics Checklist
the RISC-V Assembly Programmer's Manual lists zext.b rd, rs as andi rd, rs, 255 with the meaning Zero extend byte.
Unprivileged ISA Section 2.4.1 defines ANDI as a bitwise AND of rs1 and a sign-extended 12-bit immediate into rd.
How To Read The Expansion
Step 1
ANDI rd, rs, 255 bitwise-ANDs rs with immediate 255.
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
When To Think Of It First
Use zext.b for the table's low-8-bit zero-extension operation.
Pitfalls / Common Confusions
This is zero extension; the result is determined by ANDI's immediate-255 mask.
FAQ
What is the zext.b expansion?
The Assembly Manual lists zext.b rd, rs as andi rd, rs, 255.