zext-b

RISC-V zext-b Pseudo-Instruction Details

Assembler pseudo-instruction

Zero-extend-byte pseudo-instruction, expressible per the official assembly manual as andi rd, rs, 255. It keeps the low 8 bits and clears the high bits.

What You Write

zext.b rd, rs

Typical Real Expansion

andi rd, rs, 255

What This Pseudo Instruction Is Saving You From Writing

Byte data often needs conversion to an unsigned integer; zext.b states “keep the low 8 bits and clear the high bits” more directly than andi 255.

zext-b primarily means "Zero-extend low 8 bits". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats zext-b as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of ANDI and the other expanded instructions, not from a separate zext-b hardware opcode.

How To Read The Expansion

Step 1

ANDI with mask 255 keeps the low 8 bits and clears the upper bits.

What You May See In objdump / Disassembly

Disassembly may show either the pseudo-instruction or the expanded real instruction, depending on tool options and context.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Interpret the low 8 bits as an unsigned byte

Handle characters, byte buffers, or low-byte masks

Clear high garbage bits before bit manipulation

Pitfalls / Common Confusions

This is zero extension and does not preserve sign; signed bytes need a sign-extension path

The result range is 0..255

As a pseudo-instruction the final encoding is usually ANDI

FAQ

Is zext-b a real RISC-V instruction?

zext-b is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using zext-b?