jalr
RISC-V jalr Assembler Alias Details
Assembler alias (one-register jalr)RISC-V jalr rs is an assembler alias for jalr x1, rs, 0. JALR adds a sign-extended 12-bit immediate to rs1, clears target bit zero, and writes pc+4 to rd.
What You Write
jalr rs
Typical Real Expansion
jalr x1, rs, 0
What This Assembler Alias Saves You From Writing
The assembly manual defines this alias for one-register jalr with rd fixed to x1 and immediate fixed to zero.
How To Read The Expansion
Step 1
jalr rs expands to jalr x1, rs, 0.
Step 2
The underlying JALR writes pc+4 to rd.
Assembly Forms And Real Instructions
This page covers only the jalr rs alias; full JALR is a real instruction.
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
When To Think Of It First
Read or write the one-register jalr rs form.
Pitfalls / Common Confusions
This alias fixes rd=x1 and immediate zero; the full JALR instruction still has general operands.
JALR clears the least-significant bit of the target address.
FAQ
Is the jalr on this page a real instruction?
This page covers the jalr rs alias, which expands to jalr x1, rs, 0. Full JALR is a real instruction.