sgtz

RISC-V sgtz Pseudo-Instruction Details

Assembler pseudo-instruction

RISC-V sgtz pseudo-instruction expands to slt rd, x0, rs. SLT is a signed comparison; this form writes 1 to rd when rs is greater than zero, otherwise 0.

What You Write
sgtz rd, rs
Typical Real Expansion
slt rd, x0, rs

What This Pseudo Instruction Is Saving You From Writing

Writes a common sign test as a readable pseudo-instruction, using SLT with x0 to produce a 0/1 Boolean result.

sgtz is assembler shorthand. Read its official slt rd, x0, rs expansion and use the ISA definition of SLT for its behavior.

Official Semantics Checklist

The official assembly manual treats sgtz as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.
The real semantics come from the ISA definitions of SLT and the other expanded instructions, not from a separate sgtz hardware opcode.

How To Read The Expansion

Step 1
Assembler expands to slt rd, x0, rs

Assembly Forms And Real Instructions

The RISC-V Assembly Programmer's Manual gives the expansion slt rd, x0, rs.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

When To Think Of It First

Need rd to be 1 when rs is signed-greater-than zero
Use the official assembly spelling sgtz rd, rs

Pitfalls / Common Confusions

SGTZ expands through the signed comparison SLT.
SLT writes 1 when rs1 is less than rs2, otherwise 0.

FAQ

Is sgtz a real RISC-V instruction?

sgtz is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using sgtz?

Uses signed SLT; use SLTU-related forms for unsigned tests