RISC-V Pseudo-Instruction And Assembly Form Reference

Chapter 26 of the RISC-V Assembly Programmer's Manual lists call symbol and call rd, symbol as assembler pseudoinstructions for calling a far-away subroutine. call symbol implicitly uses ra as the link register to save the return address, while call rd, symbol uses the specified rd instead. The psABI associates the AUIPC+JALR pair generated by CALL with R_RISCV_CALL or R_RISCV_CALL_PLT.

RISC-V j is written as j offset in the RISC-V Assembly Programmer's Manual and expands to jal x0, offset. The Unprivileged ISA identifies J as the JAL assembler pseudo-instruction with rd=x0.

The RISC-V Assembly Programmer's Manual lists two la expansions: AUIPC plus ADDI with .option nopic, and AUIPC plus a GOT-based l{w|d} load with .option pic.

RISC-V li is written as li rd, immediate in the RISC-V Assembly Programmer's Manual and means Load immediate. Its expansion is listed as Myriad sequences, with different sequences possible for a numeric value.

RISC-V mv is written as mv rd, rs in the RISC-V Assembly Programmer's Manual and expands to addi rd, rs, 0. The Unprivileged ISA states that ADDI rd, rs1, 0 implements MV.

The RISC-V nop pseudo-instruction has the nop expansion ADDI x0, x0, 0, the canonical NOP encoding. It does not change architecturally visible state apart from PC advance and applicable counters.

The RISC-V ret pseudo-instruction has the ret expansion JALR x0, x1, 0 and means return from subroutine. JALR forms its target from rs1 plus a sign-extended 12-bit immediate and clears the low bit.

The RISC-V beqz pseudo-instruction has the beqz expansion BEQ rs, x0, offset and branches if the register equals zero. Its conditional branch range is plus or minus 4 KiB.

The RISC-V bnez pseudo-instruction has the bnez expansion BNE rs, x0, offset and branches if the register is not equal to zero. Its conditional branch range is plus or minus 4 KiB.

jr expands to jalr x0, rs, 0. JALR forms its target from rs plus a sign-extended 12-bit immediate and clears target bit zero.

tail symbol is a pseudoinstruction for a far-away subroutine tail call. Its default base instructions are auipc x6, offset[31:12] and jalr x0, x6, offset[11:0]; with Zicfilp, x7 is used as a scratch register.

neg expands to sub rd, x0, rs. SUB computes zero minus rs, ignores overflow, and writes the low XLEN result bits to rd.

RISC-V not pseudo-instruction expands to xori rd, rs, -1. XORI applies bitwise XOR with a sign-extended 12-bit immediate; -1 performs bitwise logical inversion and writes rd.

RISC-V seqz pseudo-instruction expands to sltiu rd, rs, 1. SLTIU is an unsigned comparison; this form writes 1 to rd only when rs is zero, otherwise 0.

RISC-V snez pseudo-instruction expands to sltu rd, x0, rs. SLTU is an unsigned comparison; this form writes 1 to rd only when rs is not zero, otherwise 0.

RISC-V lga rd, symbol is an assembler pseudoinstruction for a global-symbol address. Its documented sequence is AUIPC plus a GOT load: ld on RV64 and lw on RV32.

RISC-V lla rd, symbol is an assembler pseudoinstruction for a local-symbol address. It uses AUIPC and a PC-relative low immediate, expanding to AUIPC plus ADDI.

RISC-V sgtz pseudo-instruction expands to slt rd, x0, rs. SLT is a signed comparison; this form writes 1 to rd when rs is greater than zero, otherwise 0.

RISC-V sltz pseudo-instruction expands to slt rd, rs, x0. SLT is a signed comparison; this form writes 1 to rd when rs is less than zero, otherwise 0.

The RISC-V csrr pseudo-instruction has the csrr expansion CSRRS rd, csr, x0 for read CSR. With rs1 as x0 it does not write the CSR, though read side effects may occur.

csrw expands to csrrw x0, csr, rs. rd=x0 does not read the CSR.

csrc expands to csrrc x0, csr, rs. CSRRC clears writable CSR bits selected by rs and writes the old value to x0.

csrs expands to csrrs x0, csr, rs. CSRRS sets writable CSR bits selected by rs and writes the old value to x0.

RISC-V csrci expands to csrrci x0, csr, imm. Its zero-extended uimm clears writable CSR bits.

RISC-V csrsi expands to csrrsi x0, csr, imm. Its zero-extended uimm sets writable CSR bits.

RISC-V csrwi expands to csrrwi x0, csr, imm. Its zero-extended uimm writes the CSR.

bgez expands to bge rs, x0, offset. BGE is signed and uses a B-type offset.

bgt expands to blt rt, rs, offset. It reverses BLT operands.

bgtu expands to bltu rt, rs, offset. It branches when rs is greater than rt under unsigned comparison.

bgtz expands to blt x0, rs, offset. It branches when rs is greater than zero under signed comparison.

ble expands to bge rt, rs, offset. It branches when rs is less than or equal to rt under signed comparison.

bleu expands to bgeu rt, rs, offset. It branches when rs is less than or equal to rt under unsigned comparison.

blez expands to bge x0, rs, offset. It branches when rs is less than or equal to zero under signed comparison.

bltz expands to blt rs, x0, offset. BLT branches when rs is less than x0 under signed comparison.

frflags expands to csrrs rd, fflags, x0. fflags is the accrued exception field at fcsr bits 4:0.

fsflags uses CSRRW forms for fflags at fcsr bits 4:0.

RISC-V frcsr is an Assembly Manual v0.0.1 pseudo-instruction. It expands to csrrs rd, fcsr, x0; ISA Section 21.2 says it copies fcsr into integer register rd.

RISC-V frrm is an Assembly Manual v0.0.1 pseudo-instruction. It expands to csrrs rd, frm, x0; ISA Section 21.2 copies frm into rd's low three bits.

fscsr expands to CSRRW to write fcsr. The two-operand form reads and returns the old value only when rd is not x0; the one-operand form uses x0.

RISC-V fsflagsi uses CSRRWI to write fflags with a five-bit zero-extended immediate. It reads and returns the old value only when rd is not x0.

fsrm uses CSRRW to write the low three bits of rs to frm. It reads and returns the old value only when rd is not x0; rd=x0 and the one-operand form do not read frm.

RISC-V fsrmi is an assembler pseudoinstruction for frm: fsrmi rd, imm expands to csrrwi rd, frm, imm, while fsrmi imm uses x0; the CSR immediate field is five bits.

RISC-V jal offset is an assembler alias for jal x1, offset. JAL writes pc+4 to rd and uses a signed, two-byte-multiple offset with a plus-or-minus 1 MiB range.

RISC-V jalr rs is an assembler alias for jalr x1, rs, 0. JALR adds a sign-extended 12-bit immediate to rs1, clears target bit zero, and writes pc+4 to rd.

The RISC-V sext.w pseudo-instruction expands to addiw rd, rs, 0. This RV64I form writes the sign extension of rs's low 32 bits to rd.

RISC-V negw is an RV64 assembler pseudo-instruction that expands to subw rd, x0, rs. SUBW subtracts in the low 32 bits, then sign-extends the 32-bit result to XLEN.

RISC-V rdcycle is the pseudo-instruction for the cycle CSR and expands to csrrs rd, cycle, x0. It reads the low XLEN bits; when XLEN is at least 64, it reads the full 64-bit counter.

RISC-V rdcycleh is the pseudo-instruction for the cycle high half and expands to csrrs rd, cycleh, x0. It exists only when XLEN=32 and reads bits 63 through 32 of the same 64-bit cycle counter.

RISC-V rdinstret is the pseudo-instruction for the instret CSR and expands to csrrs rd, instret, x0. It reads the low XLEN bits; instret counts instructions retired by this hart from an arbitrary past start point.

The RISC-V rdinstreth pseudo-instruction expands to csrrs rd, instreth, x0 and, only on RV32, reads bits 63:32 of the instret counter.

The RISC-V rdtime pseudo-instruction expands to csrrs rd, time, x0 and reads the time CSR low XLEN bits.

The RISC-V rdtimeh pseudo-instruction expands to csrrs rd, timeh, x0 and, only on RV32, reads bits 63:32 of the time counter.

The RISC-V zext.b pseudo-instruction expands to andi rd, rs, 255. ANDI bitwise-ANDs rs with a sign-extended 12-bit immediate; 255 retains the low 8 bits.

The zext.h instruction zero-extends the low 16 bits to XLEN. It is provided by the Zbb extension and also by the Zbkb extension via RV32 PACK or RV64 PACKW with rs2=x0. The Assembly Manual lists an equivalent SLLI/SRLI shift sequence.

The RISC-V zext.w pseudo-instruction expands to slli rd, rs, XLEN - 32 then srli rd, rd, XLEN - 32 to zero-extend a word. On RV64 with Zba available, the table has a single-instruction form.

The Assembly Manual lists pause as the PAUSE-hint assembly spelling for fence w, 0. The Unprivileged ISA defines PAUSE as a Zihintpause HINT instruction that indicates the current hart should temporarily reduce or pause its instruction-retirement rate; the effect duration is bounded and may be zero.

RISC-V sbreak is the previous name of EBREAK; the specification says they have the same functionality and encoding, and EBREAK is used to return control to a debugging environment.

RISC-V scall is the previous name of ECALL; the specification says they have the same functionality and encoding, and ECALL is used to make a service request to the execution environment.

RISC-V FENCE.TSO is a real FENCE spelling with fm=1000, pred=RW, succ=RW; non-AMO store-to-load remains unordered.