csrw

RISC-V csrw Pseudo-Instruction Details

Assembler pseudo-instruction

Write-CSR pseudo-instruction, expanding to csrrw x0, csr, rs. It writes rs to the CSR and does not read or return the old CSR value because rd=x0.

What You Write

csrw csr, rs

Typical Real Expansion

csrrw x0, csr, rs

What This Pseudo Instruction Is Saving You From Writing

CSRRS/CSRRC/CSRRW combine read and write effects; this pseudo-instruction fixes rd or rs to x0 so read-only, write-only, set-only, or clear-only intent is clearer.

csrw primarily means "Write CSR without returning old value". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats csrw as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of CSRRW and the other expanded instructions, not from a separate csrw hardware opcode.

CSR read, write, set, clear, and immediate behavior follows the Zicsr CSRRW/CSRRS/CSRRC instructions and their immediate variants.

How To Read The Expansion

Step 1

Assembler expands to csrrw x0, csr, rs

What You May See In objdump / Disassembly

Disassembly may show the CSR pseudo name or the corresponding CSRRS/CSRRC/CSRRW real instruction.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Read or modify status registers

Write low-level privilege-related code

Make CSR-operation intent clearer than the underlying read-modify-write instruction

Pitfalls / Common Confusions

Whether a CSR exists, is writable, and which privilege level is required is defined by the Privileged ISA or the relevant extension; the pseudo-instruction does not bypass checks

The immediate forms have only a 5-bit unsigned immediate field, not an arbitrary XLEN constant

CSR writes can have side effects; do not treat them like ordinary memory-variable assignments

FAQ

Is csrw a real RISC-V instruction?

csrw is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using csrw?