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csrci

RISC-V csrci Pseudo-Instruction Details

Assembler pseudoinstruction

RISC-V csrci expands to csrrci x0, csr, imm. Its zero-extended uimm clears writable CSR bits.

What You Write
csrci csr, imm
Typical Real Expansion
csrrci x0, csr, imm

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 30 Table 6
RISC-V Unprivileged ISA Manual 20260120, Section 6.1

FAQ

How is the csrci immediate interpreted?

CSRRCI zero-extends its 5-bit uimm to XLEN bits and uses that value as the mask for clearing writable CSR bits.

Does csrci still access the CSR when uimm=0?

CSRRCI still reads the CSR and causes any read side effects. With uimm=0, it does not write the CSR or cause CSR-write side effects. rd=x0 discards the read result without suppressing the read.