RISC-V csrci Pseudo-Instruction Details
Assembler pseudo-instructionImmediate clear-CSR-bits pseudo-instruction, expanding to csrrci x0, csr, uimm. It clears CSR bits selected by 1 bits in the 5-bit immediate and does not return the old value.
What This Pseudo Instruction Is Saving You From Writing
CSRRS/CSRRC/CSRRW combine read and write effects; this pseudo-instruction fixes rd or rs to x0 so read-only, write-only, set-only, or clear-only intent is clearer.
Official Semantics Checklist
How To Read The Expansion
What You May See In objdump / Disassembly
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
When To Think Of It First
Pitfalls / Common Confusions
FAQ
Is csrci a real RISC-V instruction?
csrci is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.
What is the main trap when using csrci?
Whether a CSR exists, is writable, and which privilege level is required is defined by the Privileged ISA or the relevant extension; the pseudo-instruction does not bypass checks