csrwi
RISC-V csrwi Pseudo-Instruction Details
Assembler pseudoinstructionRISC-V csrwi expands to csrrwi x0, csr, imm. Its zero-extended uimm writes the CSR.
What You Write
csrwi csr, imm
Typical Real Expansion
csrrwi x0, csr, imm
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
FAQ
How is the csrwi immediate interpreted?
CSRRWI zero-extends its 5-bit uimm to XLEN bits and writes that value to the CSR.
Does csrwi skip the CSR write when uimm=0?
No. CSRRWI performs a CSR write even with uimm=0; it does not use the zero-mask write suppression of CSRRSI/CSRRCI. csrwi fixes rd=x0, so it does not read the CSR or cause CSR-read side effects.