ret
RISC-V ret Pseudo-Instruction Details
Assembler pseudo-instructionThe RISC-V ret pseudo-instruction has the ret expansion JALR x0, x1, 0 and means return from subroutine. JALR forms its target from rs1 plus a sign-extended 12-bit immediate and clears the low bit.
What You Write
ret
Typical Real Expansion
jalr x0, x1, 0
What This Pseudo Instruction Is Saving You From Writing
Assembly Manual lists this pseudo-instruction form.
How To Read The Expansion
Step 1
Assembly Manual expands ret to jalr x0, x1, 0.
Assembly Forms And Real Instructions
The RISC-V Assembly Programmer's Manual lists ret as JALR x0, x1, 0.
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
FAQ
What does ret expand to?
the RISC-V Assembly Programmer's Manual gives ret as jalr x0, x1, 0.