jr
RISC-V jr Pseudo-Instruction Details
Assembler pseudo-instructionjr expands to jalr x0, rs, 0. JALR forms its target from rs plus a sign-extended 12-bit immediate and clears target bit zero.
What You Write
jr rs
Typical Real Expansion
jalr x0, rs, 0
What This Pseudo Instruction Is Saving You From Writing
A JALR spelling with rd fixed to x0 and the immediate fixed to zero.
How To Read The Expansion
Step 1
jalr x0, rs, 0
Step 2
JALR writes pc+4 to x0, so the link value is discarded.
Assembly Forms And Real Instructions
The expansion above identifies the JALR ISA semantics that apply.
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
Pitfalls / Common Confusions
JALR clears the least-significant bit of its computed target.
A target that violates instruction-address alignment can raise an instruction-address-misaligned exception; this exception is not possible when IALIGN=16.
FAQ
What is the official jr expansion?
jalr x0, rs, 0