RISC-V jr Pseudo-Instruction Details

Assembler pseudo-instruction

Register-indirect jump pseudo-instruction, commonly expanded as jalr x0, 0(rs). It does not save a return address; it only transfers control to the target address held in a register.

What You Write

jr rs / jr offset(rs)

Typical Real Expansion

jalr x0, 0(rs) # or with offset: jalr x0, offset(rs)

What This Pseudo Instruction Is Saving You From Writing

Expresses unlinked indirect-jump semantics more clearly than jalr x0, 0(rs). Unlike ret, jr is a general indirect jump; ret specifically returns via ra.

jr primarily means "Indirect jump via register, no link". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats jr as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of JALR and the other expanded instructions, not from a separate jr hardware opcode.

How To Read The Expansion

Step 1

No offset: assembler expands to jalr x0, 0(rs). JALR uses rs+0 as target, writes PC+4 to x0 (discarded).

Step 2

With offset: assembler expands to jalr x0, offset(rs). Target = rs + signed 12-bit offset.

What You May See In objdump / Disassembly

jalr x0, 0(rs) may be shown as jr rs; the offset form as jr offset(rs). jr ra and ret have identical encoding but different semantics.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Indirect transfers for jump tables or computed goto

No-link jumps in dispatchers, interpreters, or state machines

Tail dispatch when return handling is already arranged elsewhere

Pitfalls / Common Confusions

jr does not write a return address; use a linking JALR form for an indirect call that must return

JALR clears the least-significant bit of the computed target address, so bit 0 is not part of the jump address

The target must meet the implementation's instruction-address alignment requirements, or real JALR semantics can raise an instruction-address-misaligned exception

FAQ

Is jr a real RISC-V instruction?

jr is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using jr?