RISC-V frflags Pseudo-Instruction Details

Assembler pseudo-instruction

frflags expands to csrrs rd, fflags, x0. fflags is the accrued exception field at fcsr bits 4:0.

What You Write

frflags rd

Typical Real Expansion

csrrs rd, fflags, x0

What This Pseudo Instruction Is Saving You From Writing

An assembler spelling for accessing fflags.

How To Read The Expansion

Step 1

csrrs rd, fflags, x0

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 30 Table 6

RISC-V Unprivileged ISA Manual 20260120, Section 6.1

FAQ

What is the official expansion of frflags?

frflags rd expands to csrrs rd, fflags, x0.