RISC-V fsflags Pseudo-Instruction Details
Assembler pseudo-instructionWrite-fflags pseudo-instruction. The common read/write form expands to csrrw rd, fflags, rs; an x0 form does not return old exception flags.
What This Pseudo Instruction Is Saving You From Writing
Floating-point state is accessed through CSR instructions; these pseudo-instructions name common fcsr/frm/fflags read and write forms for more readable floating-point environment code.
Official Semantics Checklist
Availability And Extension Conditions
- Requires the related floating-point state CSRs
- Accesses fflags/frm/fcsr through Zicsr instructions
- The target ISA/ABI environment supports the relevant floating-point extension and CSR access
- Writing frm, fflags, or fcsr can affect later floating-point results or exception flags.
How To Read The Expansion
What You May See In objdump / Disassembly
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
When To Think Of It First
Pitfalls / Common Confusions
FAQ
Is fsflags a real RISC-V instruction?
fsflags is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.
What is the main trap when using fsflags?
These pseudo-instructions require the implementation to support the related floating-point state; do not assume availability without the relevant extension