RISC-V fsflagsi Pseudo-Instruction Details
Assembler pseudo-instructionRISC-V fsflagsi uses CSRRWI to write fflags with a five-bit zero-extended immediate. It reads and returns the old value only when rd is not x0.
- fsflagsi rd, imm
- csrrwi rd, fflags, imm
- fsflagsi imm
- csrrwi x0, fflags, imm
What This Pseudo Instruction Is Saving You From Writing
fsflagsi rd, imm reads the old fflags value and returns it in rd only when rd is not x0. With rd=x0, including the one-operand form, it writes without reading fflags.
Availability And Extension Conditions
- Applies where the described fflags field is implemented.
How The Two Forms Differ
Assembly Forms And Real Instructions
Official References And Reading Order
This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.
When To Think Of It First
Pitfalls / Common Confusions
FAQ
Is fsflagsi a separate hardware opcode?
No. the RISC-V Assembly Programmer's Manual lists fsflagsi as an assembler pseudoinstruction; behavior comes from the listed CSR expansion.
What is the official fsflagsi expansion?
the RISC-V Assembly Programmer's Manual lists: csrrwi rd, fflags, imm; csrrwi x0, fflags, imm.
Does the two-operand fsflagsi form always keep the old value?
CSRRWI reads the old fflags value and returns it in rd only when rd is not x0. With rd=x0, the two-operand form, like the one-operand form, does not read fflags or cause CSR-read side effects.