fence-tso

RISC-V fence.tso FENCE Encoding Details

FENCE encoding spelling

fence.tso is a TSO memory-ordering spelling encoded as the FENCE TSO/fm=1000, pred=rw, succ=rw form. It expresses TSO-style ordering and is not merely the ordinary textual form fence rw,rw.

What You Write

fence.tso

Encoding Form

fence.tso # FENCE encoding: fm=1000, pred=rw, succ=rw

What This Encoding Spelling Expresses

Provides the standard FENCE encoding for TSO-style ordering, making a more specific memory-ordering intent portable compared with a plain fence rw,rw.

fence.tso expresses the TSO-style ordering form of FENCE. Read it through the FENCE encoding fields and the Unprivileged ISA memory-model semantics, not as an extra hardware opcode.

Official Semantics Checklist

fence.tso is the standard TSO encoding spelling of FENCE; this pseudo section includes it to explain assembly and disassembly spelling.

Its behavior comes from the Unprivileged ISA definitions of FENCE/FENCE.TSO and RVWMO, not from an extra fence-tso hardware opcode.

It uses fm=1000, pred=rw, succ=rw; do not treat it as a mere textual synonym for ordinary fm=0000 fence rw,rw.

Availability And Extension Conditions

Base Conditions

FENCE instruction encoding space
RVWMO memory-model semantics

Single-Instruction Or Standard Form

Uses the FENCE TSO encoding with fm=1000, pred=rw, succ=rw

Fallback / Boundary

An implementation may conservatively execute stronger ordering, but source semantics should still be read as FENCE.TSO.

Notes

Not an extra fence-tso opcode; it is the standard assembly spelling of a FENCE form.

How To Read The Expansion

Step 1

FENCE uses pred=rw, succ=rw, and the fm=1000 TSO encoding; it is not the ordinary fm=0000 fence rw,rw.

What You May See In objdump / Disassembly

Disassemblers usually show fence.tso; conservative implementations may execute it as the stronger fence rw,rw.

Official References And Reading Order

This page treats fence.tso as the standard assembly spelling of a FENCE encoding: read the encoding fields first, then use the Unprivileged ISA FENCE/FENCE.TSO and RVWMO sections for ordering semantics.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Express TSO-style ordering in concurrent code

Read memory-barrier sequences emitted by compilers or runtime libraries

Distinguish TSO fence from ordinary fence rw,rw encoding and semantic intent

Pitfalls / Common Confusions

fence.tso is an assembly spelling of a real FENCE encoding, not a textual synonym for ordinary fence rw,rw

An implementation may conservatively execute stronger ordering, but source semantics should still be read as a TSO fence

Memory-model code should be reviewed with RVWMO/extension specs, not by the pseudo name alone

FAQ

Is fence-tso a real RISC-V instruction?

fence.tso is the TSO encoding spelling of the FENCE instruction, not an extra fence-tso hardware opcode. The expansion/encoding fields on this page explain how real FENCE semantics execute it.

What is the main trap when using fence-tso?