pause

RISC-V pause Pseudo-Instruction Details

Assembler pseudo-instruction

PAUSE hint pseudo-instruction, listed in the official assembly manual as fence w, 0. It is used in spin-wait loops to give implementations an opportunity to reduce resource contention or power.

What You Write

pause

Typical Real Expansion

fence w, 0

What This Pseudo Instruction Is Saving You From Writing

Busy-wait loops do not always need a real memory barrier; pause expresses “I am waiting” with a standard hint encoding so hardware or simulators may optimize handling.

pause primarily means "Spin-wait hint". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats pause as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of FENCE and the other expanded instructions, not from a separate pause hardware opcode.

pause is a hint-style form; do not treat it as changing program-visible state or as providing synchronization semantics.

Availability And Extension Conditions

Base Conditions

Zihintpause hint semantics
Encoded as FENCE w,0

Single-Instruction Or Standard Form

The target environment accepts the PAUSE hint spelling

Fallback / Boundary

An implementation may treat PAUSE as a low-cost hint or NOP-like operation; it does not guarantee yielding the CPU or a fixed delay.

Notes

Not a general synchronization primitive; use suitable fence/AMO/aq/rl operations when ordering is required.

How To Read The Expansion

Step 1

FENCE w,0 encodes the PAUSE hint, indicating the hart is in a spin-wait loop.

What You May See In objdump / Disassembly

Tools may show pause or the underlying fence w,0. As a HINT, the exact effect is implementation-dependent.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

RISC-V Unprivileged ISA Manual

When To Think Of It First

Inside lock, spin-wait, or polling loops

Wait for another hart or device to update state

Reduce pressure from busy-wait loops on pipeline, power, or shared resources

Pitfalls / Common Confusions

pause is a hint; it does not guarantee sleep, CPU yield, or a fixed delay

It is not a general memory-synchronization primitive; use suitable fence/AMO/aq/rl when ordering is required

Different implementations may treat it as a low-cost NOP

FAQ

Is pause a real RISC-V instruction?

pause is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using pause?