pause

RISC-V PAUSE HINT Instruction Details

Zihintpause PAUSE HINT instruction (assembly spelling: pause)

The Assembly Manual lists pause as the PAUSE-hint assembly spelling for fence w, 0. The Unprivileged ISA defines PAUSE as a Zihintpause HINT instruction that indicates the current hart should temporarily reduce or pause its instruction-retirement rate; the effect duration is bounded and may be zero.

What You Write

pause

Encoding Form

fence w, 0

PAUSE HINT ISA Semantics

pause is the fence w, 0 spelling of the Zihintpause PAUSE HINT instruction.

Availability And Extension Conditions

Base Conditions

Zihintpause extension
PAUSE is encoded in the FENCE opcode

Single-Instruction Or Standard Form

PAUSE HINT encoding

Fallback / Boundary

The PAUSE effect is bounded and may be zero.

Notes

PAUSE mandates no particular memory ordering.

How To Read The Expansion

Step 1

The FENCE encoding pred=W, succ=0, fm=0, rd=x0, rs1=x0 is the PAUSE HINT.

Official References And Reading Order

RISC-V Assembly Programmer's Manual Table 5 lists pause as the PAUSE-hint spelling for fence w, 0; Chapter 9 of the Unprivileged ISA defines PAUSE as a Zihintpause HINT instruction and specifies its FENCE encoding.

RISC-V Assembly Programmer's Manual v0.0.1, Chapter 29 Table 5

RISC-V Unprivileged ISA Manual 2026-01-20, Chapter 9

FAQ

Is PAUSE a RISC-V instruction?

Yes. Chapter 9 of the Unprivileged ISA defines PAUSE as a Zihintpause HINT instruction. the RISC-V Assembly Programmer's Manual lists pause as the assembly spelling for fence w, 0; the ISA specifies that PAUSE is encoded within the FENCE opcode.

What is the main trap when using pause?

It mandates no particular memory ordering, and its effect duration may be zero.