nop

RISC-V nop Pseudo-Instruction Details

Assembler pseudo-instruction

No-operation pseudo-instruction, expands to addi x0, x0, 0. Changes no architectural state except advancing PC. Primarily used for code alignment, icache line padding, and runtime code patch reservation.

What You Write

nop

Typical Real Expansion

addi x0, x0, 0

What This Pseudo Instruction Is Saving You From Writing

Provides the canonical NOP encoding defined by the ISA manual — addi x0, x0, 0 writes 0 to x0 (discarded by hardware), with the only architecturally visible effect being PC advancement.

nop primarily means "No operation; only advances PC". It is assembler-level shorthand; when debugging, auditing, or reading machine code, reason from the real expansion and relocation semantics listed on this page.

Official Semantics Checklist

The official assembly manual treats nop as an assembler-level pseudo-instruction or alias; hardware executes the expanded real instruction sequence.

The real semantics come from the ISA definitions of ADDI and the other expanded instructions, not from a separate nop hardware opcode.

How To Read The Expansion

Step 1

addi x0, x0, 0: writes the result of x0 + 0 to x0.

Step 2

x0 is hardwired to 0, so the written value is discarded. Sole effect: PC ← PC + 4 (or PC + 2 if compressed C.NOP).

What You May See In objdump / Disassembly

addi x0, x0, 0 shown as nop in disassembly. When encountered in the instruction stream, the CPU only advances PC with no side effects.

Official References And Reading Order

This page treats pseudo-instructions as assembler-level aliases or macros: first read what real instructions they expand to, then use the official ISA manual for the behavior of those real instructions. ABI, relocation, and linker-relaxation details follow the psABI document.

RISC-V Assembly Programmer's Manual

When To Think Of It First

Align code to specific address boundaries (4/8/16-byte alignment)

Icache line padding to align loop entries

Reserve space for runtime code patching or hotfixes

NOP sleds (not recommended for exploit mitigation)

Pitfalls / Common Confusions

NOP still occupies instruction encoding and fetch bandwidth; exact execution cost is microarchitecture-dependent, so do not assume it is free

NOP is not a compiler barrier/fence — it does not prevent compiler or CPU instruction reordering

RISC-V reserves HINT encoding space for future NOP variants (e.g., stall hints), but currently only addi x0,x0,0 is the standard NOP

FAQ

Is nop a real RISC-V instruction?

nop is an assembler pseudo-instruction or alias, not a separate hardware opcode. The “Typical Real Expansion” section lists the official expansion, and behavior is defined by the expanded ISA instructions.

What is the main trap when using nop?