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CSR Bit Fields

RISC-V hstateen0 CSR Register

Address 0x60CPrivilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hstateen0 is a hypervisor state-enable CSR.

Related Search Terms

hstateen0 CSR hstateen0 0x60C hstateen state enable hstateen0 AIA Smstateen

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

SE063WARL (always writable)C0WARL

SE063WARL (always writable)ENVCFG62WARLFCSR1WARL C0WARL

Field Map

Understand hstateen0 By Bit Fields

13 key fields

SE0

WARL (always writable)

Controls VM access to the sstateen0 CSR. Bit 63 of hstateen0 is always writable.

SE0 (bit 63) — Controls VM access to the sstateen0 CSR. Bit 63 of hstateen0 is always writable.

What This Field Controls

- Controls VM access to the sstateen0 CSR. Bit 63 of hstateen0 is always writable.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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ENVCFG

WARL

Controls VM access to the senvcfg CSR.

ENVCFG (bit 62) — Controls VM access to the senvcfg CSR.

What This Field Controls

- Controls VM access to the senvcfg CSR.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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WPRI

Write-preserve, read-ignore bit.

WPRI (bit 61) — Write-preserve, read-ignore bit.

What This Field Controls

- Write-preserve, read-ignore bit.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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CSRIND

WARL

Controls VM access to Sscsrind siselect/sireg* (really VS indirect CSR) state.

CSRIND (bit 60) — Controls VM access to Sscsrind siselect/sireg* (really VS indirect CSR) state.

What This Field Controls

- Controls VM access to Sscsrind siselect/sireg* (really VS indirect CSR) state.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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AIA

WARL

Controls VM access to Ssaia state not covered by CSRIND or IMSIC.

AIA (bit 59) — Controls VM access to Ssaia state not covered by CSRIND or IMSIC.

What This Field Controls

- Controls VM access to Ssaia state not covered by CSRIND or IMSIC.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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IMSIC

WARL

Controls VM access to guest IMSIC state, including stopei (really vstopei).

IMSIC (bit 58) — Controls VM access to guest IMSIC state, including stopei (really vstopei).

What This Field Controls

- Controls VM access to guest IMSIC state, including stopei (really vstopei).

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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CONTEXT

WARL

Controls VM access to the Sdtrig scontext CSR.

CONTEXT (bit 57) — Controls VM access to the Sdtrig scontext CSR.

What This Field Controls

- Controls VM access to the Sdtrig scontext CSR.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

56:55

WPRI

Write-preserve, read-ignore bits; P1P13 and SRMCFG are defined only in mstateen0.

WPRI (bits 56:55) — Write-preserve, read-ignore bits; P1P13 and SRMCFG are defined only in mstateen0.

What This Field Controls

- Write-preserve, read-ignore bits; P1P13 and SRMCFG are defined only in mstateen0.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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CTR

WARL

When Smctr/Ssctr state exists, controls VM access to CTR state; read-only zero when that controlled state is not implemented.

CTR (bit 54) — When Smctr/Ssctr state exists, controls VM access to CTR state; read-only zero when that controlled state is not implemented.

What This Field Controls

- When Smctr/Ssctr state exists, controls VM access to CTR state; read-only zero when that controlled state is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

53:3

WPRI

Write-preserve, read-ignore bits.

WPRI (bits 53:3) — Write-preserve, read-ignore bits.

What This Field Controls

- Write-preserve, read-ignore bits.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

JVT

WARL

Controls access to the Zcmt jvt CSR; read-only zero when that controlled state is not implemented.

JVT (bit 2) — Controls access to the Zcmt jvt CSR; read-only zero when that controlled state is not implemented.

What This Field Controls

- Controls access to the Zcmt jvt CSR; read-only zero when that controlled state is not implemented.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

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FCSR

WARL

Controls Zfinx-family fcsr access; it is read-only zero when misa.F=1.

FCSR (bit 1) — Controls Zfinx-family fcsr access; it is read-only zero when misa.F=1.

What This Field Controls

- Controls Zfinx-family fcsr access; it is read-only zero when misa.F=1.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

C

WARL

Controls VM access to all custom state. The C bit itself is a standard state-enable field, not custom state.

C (bit 0) — Controls VM access to all custom state. The C bit itself is a standard state-enable field, not custom state.

What This Field Controls

- Controls VM access to all custom state. The C bit itself is a standard state-enable field, not custom state.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

Official Basis & Search Notes

hstateen0 is a hypervisor state-enable CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hstateen0 address, access class, and width are checked against the official CSR tables: 0x60C, HRW, HSXLEN.

State-enable CSRs control lower-privilege or VM access to extension state; they do not affect M-mode access.

hstateen0 has official CSRIND, AIA, IMSIC, CONTEXT, ENVCFG, and related bits.

When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.

RISC-V Privileged Architecture Manual - CSR table RISC-V Privileged Architecture Manual - Hypervisor extension RISC-V Smstateen/Ssstateen extension RISC-V Advanced Interrupt Architecture CSR chapter RISC-V Smcsrind/Sscsrind indirect CSR extension

What To Check First When Reading This CSR

- hstateen0 is a Hypervisor-level CSR; its separate address is in the official HRW access class.
- Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

- When writing hstateen0, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hstateen0 be accessed through a supervisor CSR alias?

Do not treat hstateen0 as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

What do the AIA/IMSIC/CSRIND bits in hstateen0 control?

They control VM access to AIA, guest IMSIC, and indirect CSR alias state, respectively.