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CSR Bit Fields

RISC-V hstateen2 CSR Register

Address 0x60EPrivilege HypervisorAccess HRW / 64 bits on RV64; RV32 accesses the upper 32 bits through hstateen2hHypervisor and virtualization CSRs

hstateen2 is the Hypervisor State Enable 2 CSR.

Related Search Terms
hstateen2 CSRhstateen2 0x60Ehstateen2 SE2
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SE263WritableReserved62:0Read-only zero
Field Map

Understand hstateen2 By Bit Fields

2 key fields
63

SE2

Writable

Controls VS/VU access to sstateen2; this hstateen bit is always writable, not read-only.

SE2 (bit 63) — Controls VS/VU access to sstateen2; this hstateen bit is always writable, not read-only.

What This Field Controls

  • - Controls VS/VU access to sstateen2; this hstateen bit is always writable, not read-only.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
62:0

Reserved

Read-only zero

Currently undefined reserved bits read as zero.

Reserved (bits 62:0) — Currently undefined reserved bits read as zero.

What This Field Controls

  • - Currently undefined reserved bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual

What To Check First When Reading This CSR

  • - hstateen2 is defined only when both H and Smstateen are implemented.
  • - When mstateen2[63] is zero, the corresponding hstateen2 bit reads as zero.

Risk Checks Before Writing

  • - After machine software changes mstateen2, it is responsible for initializing corresponding writable hstateen2 bits to zero; hypervisor software should enable it only when prepared to manage that state.

Put It Back Into A Real Flow

1

Confirm H and Smstateen are implemented.

2

Check mstateen2[63], then configure hstateen2[63].

3

A prohibited VS/VU access raises the applicable exception specified by the architecture.