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CSR Bit Fields

RISC-V hstateen1 CSR Register

Address 0x60DPrivilege HypervisorAccess HRW / HSXLENHypervisor and virtualization CSRs

hstateen1 is a hypervisor state-enable CSR.

Related Search Terms
hstateen1 CSRhstateen1 0x60Dhstateen state enablestate enable bitsSmstateen
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
SE163WARL (always writable)Reserved62:0Read-only zero
Field Map

Understand hstateen1 By Bit Fields

2 key fields
63

SE1

WARL (always writable)

Controls VM access to the matching sstateen1 CSR. Bit 63 of hstateen1 is always writable, not read-only.

SE1 (bit 63) — Controls VM access to the matching sstateen1 CSR. Bit 63 of hstateen1 is always writable, not read-only.

What This Field Controls

  • - Controls VM access to the matching sstateen1 CSR. Bit 63 of hstateen1 is always writable, not read-only.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
62:0

Reserved

Read-only zero

The current manual defines no standard use for the remaining hstateen1 bits; undefined reserved bits read as zero.

Reserved (bits 62:0) — The current manual defines no standard use for the remaining hstateen1 bits; undefined reserved bits read as zero.

What This Field Controls

  • - The current manual defines no standard use for the remaining hstateen1 bits; undefined reserved bits read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

hstateen1 is a hypervisor state-enable CSR. It is HS/M-side hypervisor state, not a VS supervisor CSR copy; guest access is governed by the H extension and relevant state-enable, AIA, Sstc, or Smcsrind rules.

hstateen1 address, access class, and width are checked against the official CSR tables: 0x60D, HRW, HSXLEN.
State-enable CSRs control lower-privilege or VM access to extension state; they do not affect M-mode access.
hstateen1-3 bits are allocated by official extensions; unallocated bits must not be treated as ordinary VALUE.
When writing, modify only officially defined fields; handle WARL, WLRL, WPRI, and reserved fields according to the official specification and implementation behavior.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extensionRISC-V Smstateen/Ssstateen extensionRISC-V Advanced Interrupt Architecture CSR chapterRISC-V Smcsrind/Sscsrind indirect CSR extension

What To Check First When Reading This CSR

  • - hstateen1 is a Hypervisor-level CSR; its separate address is in the official HRW access class.
  • - Guest/VS software does not reach this H-level CSR through a supervisor CSR alias; access is controlled by the H extension and relevant optional-extension rules.

Risk Checks Before Writing

  • - When writing hstateen1, modify only officially defined target fields and preserve WPRI, reserved, and unchanged fields.

Put It Back Into A Real Flow

1

Confirm the current software is in an M/HS context that may access Hypervisor CSRs.

2

Confirm that the H, AIA, Sstc, Smstateen, Smcsrind, or other defining extension is implemented.

3

Read or write only official fields; whether guest-related access succeeds or traps is controlled by the corresponding extension rules and state-enable state.

FAQ

Can hstateen1 be accessed through a supervisor CSR alias?

Do not treat hstateen1 as a VS CSR copy. It is an H-level CSR; whether guest/VS access to related functionality traps is defined by the H extension and the relevant optional extension.

What do the AIA/IMSIC/CSRIND bits in hstateen0 control?

They control VM access to AIA, guest IMSIC, and indirect CSR alias state, respectively.