mctrctl (0x34E) is the 64-bit Smctr v1.0 machine control CSR for selecting recorded privilege modes, controlling external-trap/freeze behavior, and filtering control-transfer types.
Selects transfer recording in U-mode. This field is mandatory and writable.
U (bit 0) — Selects transfer recording in U-mode. This field is mandatory and writable.
U-mode recording is not selected.
U-mode recording is selected.
Selects transfer recording in S/HS-mode. This field is mandatory and writable.
S (bit 1) — Selects transfer recording in S/HS-mode. This field is mandatory and writable.
S/HS-mode recording is not selected.
S/HS-mode recording is selected.
Selects transfer recording in M-mode. This field is mandatory and writable.
M (bit 2) — Selects transfer recording in M-mode. This field is mandatory and writable.
M-mode recording is not selected.
M-mode recording is selected.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 6:3) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Enables Return Address Stack (RAS) emulation mode; when set, calls are recorded, returns pop entries, co-routine swaps act as a return plus call, other transfer types are inhibited, and bits 47:32 plus xTE are ignored.
RASEMU (bit 7) — Enables Return Address Stack (RAS) emulation mode; when set, calls are recorded, returns pop entries, co-routine swaps act as a return plus call, other transfer types are inhibited, and bits 47:32 plus xTE are ignored.
Use normal CTR recording behavior.
Enable RAS-emulation recording behavior and ignore the transfer filters and external-trap enable bits.
When S=0, allows recording external traps to S-mode.
STE (bit 8) — When S=0, allows recording external traps to S-mode.
Do not additionally permit recording external traps to S-mode.
Permit recording external traps to S-mode.
When M=0, allows recording external traps to M-mode.
MTE (bit 9) — When M=0, allows recording external traps to M-mode.
Do not additionally permit recording external traps to M-mode.
Permit recording external traps to M-mode.
Reserved. Software ignores reads and preserves this bit on writes; an undefined implementation is read-only zero.
WPRI (bit 10) — Reserved. Software ignores reads and preserves this bit on writes; an undefined implementation is read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Sets sctrstatus.FROZEN when a breakpoint exception traps to M-mode or S-mode. This field is mandatory and writable.
BPFRZ (bit 11) — Sets sctrstatus.FROZEN when a breakpoint exception traps to M-mode or S-mode. This field is mandatory and writable.
Breakpoint traps do not trigger this automatic freeze.
A qualifying breakpoint trap sets FROZEN.
Sets sctrstatus.FROZEN when an LCOFI traps to M-mode or S-mode; it must be writable when Sscofpmf is implemented.
LCOFIFRZ (bit 12) — Sets sctrstatus.FROZEN when an LCOFI traps to M-mode or S-mode; it must be writable when Sscofpmf is implemented.
LCOFI traps do not trigger this automatic freeze.
A qualifying LCOFI trap sets FROZEN.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 32:13) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Inhibits recording exceptions, except that it does not affect external-trap recording enabled through xTE.
EXCINH (bit 33) — Inhibits recording exceptions, except that it does not affect external-trap recording enabled through xTE.
Do not inhibit exception recording through this bit.
Inhibit exception recording; external traps enabled through xTE are unaffected by this bit.
Inhibits recording interrupts, except that it does not affect external-trap recording enabled through xTE.
INTRINH (bit 34) — Inhibits recording interrupts, except that it does not affect external-trap recording enabled through xTE.
Do not inhibit interrupt recording through this bit.
Inhibit interrupt recording; external traps enabled through xTE are unaffected by this bit.
Inhibits recording trap returns.
TRETINH (bit 35) — Inhibits recording trap returns.
Do not inhibit trap-return recording through this bit.
Inhibit trap-return recording.
Enables recording not-taken branches; this is an enable bit rather than an inhibit bit.
NTBREN (bit 36) — Enables recording not-taken branches; this is an enable bit rather than an inhibit bit.
Do not record not-taken branches.
Record qualifying not-taken branches.
Inhibits recording taken branches.
TKBRINH (bit 37) — Inhibits recording taken branches.
Do not inhibit taken-branch recording through this bit.
Inhibit taken-branch recording.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 39:38) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
Inhibits recording indirect calls.
INDCALLINH (bit 40) — Inhibits recording indirect calls.
Do not inhibit indirect-call recording through this bit.
Inhibit indirect-call recording.
Inhibits recording direct calls.
DIRCALLINH (bit 41) — Inhibits recording direct calls.
Do not inhibit direct-call recording through this bit.
Inhibit direct-call recording.
Inhibits recording indirect jumps without linkage.
INDJMPINH (bit 42) — Inhibits recording indirect jumps without linkage.
Do not inhibit this jump class through this bit.
Inhibit indirect jumps without linkage.
Inhibits recording direct jumps without linkage.
DIRJMPINH (bit 43) — Inhibits recording direct jumps without linkage.
Do not inhibit this jump class through this bit.
Inhibit direct jumps without linkage.
Inhibits recording co-routine swaps.
CORSWAPINH (bit 44) — Inhibits recording co-routine swaps.
Do not inhibit co-routine-swap recording through this bit.
Inhibit co-routine-swap recording.
Inhibits recording function returns.
RETINH (bit 45) — Inhibits recording function returns.
Do not inhibit function-return recording through this bit.
Inhibit function-return recording.
Inhibits recording other indirect jumps with linkage.
INDLJMPINH (bit 46) — Inhibits recording other indirect jumps with linkage.
Do not inhibit this jump class through this bit.
Inhibit other indirect jumps with linkage.
Inhibits recording other direct jumps with linkage.
DIRLJMPINH (bit 47) — Inhibits recording other direct jumps with linkage.
Do not inhibit this jump class through this bit.
Inhibit other direct jumps with linkage.
Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
WPRI (bits 59:48) — Reserved. Software ignores reads and preserves these bits on writes; undefined implementations are read-only zero.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
WARL bits for custom use; value 0 must correspond to standard behavior.
Custom[3:0] (bits 63:60) — WARL bits for custom use; value 0 must correspond to standard behavior.
This field is better understood together with surrounding context than as a fixed memorized enumeration.
mctrctl is the 64-bit top-level CTR control register: low bits select modes, RAS, external traps, and freeze behavior, while the upper half mainly filters transfer types; RV32 cannot explicitly access bits 63:32.
Confirm Smctr, S-mode, and Sscsrind are implemented.
Read mctrctl, identify implemented fields, and preserve WPRI bits.
Configure M/S/U, freeze/external-trap policy, and required transfer-type filters.
After writing, account for CCV=0 in the next record.
No. RV32 explicit access reaches only bits 31:0, and Smctr v1.0 defines no mctrctlh, so RV32 software cannot explicitly access bits 63:32.
No. Only M, S, U, and BPFRZ are mandatory; other fields are optional and read-only zero when absent. LCOFIFRZ must be writable when Sscofpmf is implemented.