CSR Bit Fields

RISC-V mctrctl CSR Register

Address 0x34EPrivilege MachineAccess MRW / XLENMachine AIA, timer, and indirect interrupt CSRs

mctrctl is the machine-level control CSR for Smctr Control Transfer Records.

Field Map

Understand mctrctl By Bit Fields

1 key fields
XLEN-1:0

MCTRCTL

MRW

Control Transfer Records control fields; detailed encodings follow the Smctr extension.

MCTRCTL (bits XLEN-1:0) — Control Transfer Records control fields; detailed encodings follow the Smctr extension.

What This Field Controls

  • - Control Transfer Records control fields; detailed encodings follow the Smctr extension.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mctrctl is listed as the Machine Control Transfer Records Control Register at 0x34E with MRW access.

The official CSR table lists mctrctl as the Machine Control Transfer Records Control Register.
This page does not classify mctrctl as AIA or an ordinary interrupt CSR.
Detailed fields should be interpreted by the Smctr extension; fields not derivable from the CSR table are not invented here.

What To Check First When Reading This CSR

  • - Check mctrctl address 0x34E and MRW access against the official CSR table.
  • - Do not assume this CSR is accessible when Smctr is not implemented.

Risk Checks Before Writing

  • - Confirm Smctr is implemented before writing, and preserve unchanged bits according to Smctr field definitions.

Put It Back Into A Real Flow

1

Confirm Smctr is implemented.

2

Read mctrctl to inspect current Control Transfer Records configuration.

3

Modify only target fields defined by Smctr.

FAQ

Is mctrctl an AIA CSR?

No. The official CSR table lists it under Machine Control Transfer Records Configuration.