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CSR Bit Fields

RISC-V sctrstatus CSR Register

Address 0x14FPrivilege SupervisorAccess RW / 32Supervisor AIA, timer, and indirect interrupt CSRs

sctrstatus (0x14F) is the 32-bit Supervisor CTR status CSR, holding CTR write-pointer and freeze state and updated by hardware when CTR is active.

Related Search Terms
sctrstatus CSRsctrstatus 0x14FCTR statusWRPTRFROZENSmctr
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
RESERVED63:32RO0FROZEN31RW / may be set by hardwareWPRI30:8WPRI / undefined RO0WRPTR7:0WARL / hardware-updated
Field Map

Understand sctrstatus By Bit Fields

4 key fields
7:0

WRPTR

WARL / hardware-updated

Indicates the physical CTR buffer entry to be written next; it increments after new transfers are recorded, with exceptions when RASEMU=1. Bits above those needed for depth-1 are read-only zero; after depth changes the value is unspecified but legal.

WRPTR (bits 7:0) — Indicates the physical CTR buffer entry to be written next; it increments after new transfers are recorded, with exceptions when RASEMU=1. Bits above those needed for depth-1 are read-only zero; after depth changes the value is unspecified but legal.

What This Field Controls

  • - Indicates the physical CTR buffer entry to be written next; it increments after new transfers are recorded, with exceptions when RASEMU=1. Bits above those needed for depth-1 are read-only zero; after depth changes the value is unspecified but legal.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
30:8

WPRI

WPRI / undefined RO0

Undefined status bits. Software ignores reads and preserves writes; undefined bits must be read-only zero unless a custom extension is implemented and enabled.

WPRI (bits 30:8) — Undefined status bits. Software ignores reads and preserves writes; undefined bits must be read-only zero unless a custom extension is implemented and enabled.

What This Field Controls

  • - Undefined status bits. Software ignores reads and preserves writes; undefined bits must be read-only zero unless a custom extension is implemented and enabled.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
31

FROZEN

RW / may be set by hardware

Inhibits transfer recording when set. Software may write it; hardware may set it when BPFRZ or LCOFIFRZ conditions are met.

FROZEN (bit 31) — Inhibits transfer recording when set. Software may write it; hardware may set it when BPFRZ or LCOFIFRZ conditions are met.

What This Field Controls

  • - Inhibits transfer recording when set. Software may write it; hardware may set it when BPFRZ or LCOFIFRZ conditions are met.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:32

RESERVED

RO0

Upper half of the RV64 CSR access width; architected sctrstatus state is only bits 31:0, so these upper bits carry no sctrstatus state and read as zero.

RESERVED (bits 63:32) — Upper half of the RV64 CSR access width; architected sctrstatus state is only bits 31:0, so these upper bits carry no sctrstatus state and read as zero.

What This Field Controls

  • - Upper half of the RV64 CSR access width; architected sctrstatus state is only bits 31:0, so these upper bits carry no sctrstatus state and read as zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

sctrstatus is the runtime-status entry point for the CTR buffer. It is hardware-updated, so writes are riskier than ordinary configuration CSR writes.

WRPTR is a WARL field that indicates the physical CTR buffer entry to be written next and changes as records are made.
FROZEN inhibits transfer recording and may be written by software or set by qualifying breakpoint or LCOFI traps.
Undefined bits are WPRI; they must be read-only zero unless a custom extension defines enabled status fields.
Logical entry 0 corresponds to the physical entry preceding WRPTR; logical/physical mapping depends on sctrdepth.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - SmctrRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements the extension containing sctrstatus; unimplemented or insufficiently privileged CSR accesses raise an illegal-instruction exception.
  • - Use address 0x14F, the lowest access privilege, and the official access class to decide whether software may access it directly.
  • - Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

  • - Hardware updates sctrstatus while CTR is active; multi-instruction read-modify-write can lose a hardware update.
  • - Before modifying sctrstatus, software should normally ensure CTR is inactive, for example FROZEN=1 or current privilege mode not enabled for recording.
  • - When restoring CTR state, write sctrstatus before restoring CTR entry state.

Put It Back Into A Real Flow

1

Read sctrstatus before reading CTR entries to determine buffer state such as WRPTR/FROZEN.

2

Make CTR inactive before modifying sctrstatus so hardware-updated state is not overwritten.

3

When saving/restoring CTR, restore sctrstatus before restoring concrete CTR entry state.

FAQ

Why stop CTR before writing sctrstatus?

Because hardware may update WRPTR/FROZEN while CTR is active, and a multi-instruction RMW can overwrite a hardware update.