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CSR Bit Fields

RISC-V sctrdepth CSR Register

Address 0x15FPrivilege SupervisorAccess RW / 32Supervisor AIA, timer, and indirect interrupt CSRs

sctrdepth (0x15F) is the 32-bit Supervisor CTR depth CSR; its WARL DEPTH field selects the CTR buffer depth.

Related Search Terms
sctrdepth CSRsctrdepth 0x15FCTR depthDEPTH fieldSmctrCTR buffer
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
NotPartOfCSR63:32N/AWPRI31:3WPRIDEPTH2:0WARL
Field Map

Understand sctrdepth By Bit Fields

3 key fields
2:0

DEPTH

WARL

Selects CTR buffer depth: 000=16, 001=32, 010=64, 011=128, 100=256, 11x reserved; implementations may support only a subset.

DEPTH (bits 2:0) — Selects CTR buffer depth: 000=16, 001=32, 010=64, 011=128, 100=256, 11x reserved; implementations may support only a subset.

What This Field Controls

  • - Selects CTR buffer depth: 000=16, 001=32, 010=64, 011=128, 100=256, 11x reserved; implementations may support only a subset.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
31:3

WPRI

WPRI

Undefined bits are WPRI.

WPRI (bits 31:3) — Undefined bits are WPRI.

What This Field Controls

  • - Undefined bits are WPRI.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
63:32

NotPartOfCSR

N/A

sctrdepth is a 32-bit CSR; bits 63:32 in an RV64 display are not defined bits of this CSR.

NotPartOfCSR (bits 63:32) — sctrdepth is a 32-bit CSR; bits 63:32 in an RV64 display are not defined bits of this CSR.

What This Field Controls

  • - sctrdepth is a 32-bit CSR; bits 63:32 in an RV64 display are not defined bits of this CSR.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

sctrdepth determines the effective number of CTR buffer entries. Logical entries beyond the current depth read as zero and are read-only.

DEPTH is WARL; encodings 000..100 correspond to 16..256 entries.
When depth is increased, newly accessible entries contain unspecified but legal values.
When mstateen0.CTR=0, accesses to sctrdepth below M-mode raise illegal-instruction exceptions.
The specification expects OSs to access it mostly at boot; frequent access can increase virtualization overhead.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - SmctrRISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - First confirm that the hart implements Smctr/Ssctr and that Smstateen has not blocked S-mode access to CTR state through mstateen0.CTR.
  • - Use address 0x15F, the lowest access privilege, and the official access class to decide whether software may access it directly.
  • - Do not assume fixed values for reserved, WPRI, WARL, or WLRL fields; interpret them according to the specification and implementation.

Risk Checks Before Writing

  • - Implementations may support only a subset of DEPTH encodings; read back after writing to confirm the actual value.
  • - VS/VU-mode accesses to sctrdepth raise a virtual-instruction exception; hstateen0.CTR does not enable sctrdepth because the specification always traps VS/VU accesses.

Put It Back Into A Real Flow

1

Choose the desired buffer depth during OS boot or CTR initialization.

2

After writing DEPTH, read it back to confirm the actual WARL value accepted.

3

Interpret logical CTR entries according to the actual depth; logical entries beyond the depth read as zero and are read-only.

FAQ

Does sctrdepth support every depth?

Not necessarily. DEPTH is WARL, and supported values are implementation-specific.