RISC-V mhpmcounter18 CSR Register

Address 0xB12Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter18 at 0xB12 is machine hardware performance-monitor counter 18, with up to 64 bits of precision for the event selected by mhpmevent18.

Related Search Terms

mhpmcounter18 CSR mhpmcounter18 0xB12 HPM counter 18 mhpmevent18 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter18 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent18; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent18 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent18; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent18 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent18; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent18 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter18 is machine HPM counter 18. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent18.

The official machine HPM mechanism defines mhpmcounter18 as a WARL counter with up to 64 bits of precision.

mhpmevent18 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter18h accesses bits 63:32; a legal implementation may make both mhpmcounter18 and mhpmevent18 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter18 is selected by mhpmevent18; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter18 view are controlled by mcounteren.HPM18; U-mode is additionally controlled by scounteren.HPM18.
- On RV32, mhpmcounter18h accesses bits 63:32 of mhpmcounter18.

Risk Checks Before Writing

- Writing mhpmcounter18 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM18 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent18 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent18 to select the platform-defined event to count.

Set mcountinhibit.HPM18 when needed to stop mhpmcounter18 from incrementing.

Read mhpmcounter18; on RV32, also read mhpmcounter18h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter18 be accessed from any privilege level?

No. The CSR table lists mhpmcounter18 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter18 view: S/U-mode reads are controlled by mcounteren.HPM18, and U-mode reads are additionally controlled by scounteren.HPM18. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter18 related to hpmcounter18?

mhpmcounter18 is the machine read/write counter; hpmcounter18 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM18, and U-mode reads are additionally controlled by scounteren.HPM18.