RISC-V mhpmcounter21 CSR Register

Address 0xB15Privilege MachineAccess RW / Up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter21 at 0xB15 is machine hardware performance-monitor counter 21, with up to 64 bits of precision for the event selected by mhpmevent21.

Related Search Terms

mhpmcounter21 CSR mhpmcounter21 0xB15 HPM counter 21 mhpmevent21 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter21 By Bit Fields

1 key fields

63:0

COUNT

Machine HPM count for the event selected by mhpmevent21; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent21 selector both read-only zero.

COUNT (bits 63:0) — Machine HPM count for the event selected by mhpmevent21; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent21 selector both read-only zero.

What This Field Controls

- Machine HPM count for the event selected by mhpmevent21; this is a WARL register with up to 64 bits of precision, and a legal implementation may make it and the corresponding mhpmevent21 selector both read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter21 is machine HPM counter 21. It does not define event meaning itself; with up to 64 bits of precision, it counts the platform-defined event currently selected by mhpmevent21.

The official machine HPM mechanism defines mhpmcounter21 as a WARL counter with up to 64 bits of precision.

mhpmevent21 selects the event; event meaning is platform-defined, and event 0 means "no event".

On RV32, mhpmcounter21h accesses bits 63:32; a legal implementation may make both mhpmcounter21 and mhpmevent21 read-only zero.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter21 is selected by mhpmevent21; event meaning is platform-defined.
- S/U-mode reads of the read-only hpmcounter21 view are controlled by mcounteren.HPM21; U-mode is additionally controlled by scounteren.HPM21.
- On RV32, mhpmcounter21h accesses bits 63:32 of mhpmcounter21.

Risk Checks Before Writing

- Writing mhpmcounter21 changes its current count; a CSR write takes effect after the writing instruction has otherwise completed.
- mcountinhibit.HPM21 controls whether this counter increments, not its accessibility.
- This counter and mhpmevent21 are WARL; event encodings are platform-defined, and event 0 means "no event".

Put It Back Into A Real Flow

Configure mhpmevent21 to select the platform-defined event to count.

Set mcountinhibit.HPM21 when needed to stop mhpmcounter21 from incrementing.

Read mhpmcounter21; on RV32, also read mhpmcounter21h to obtain the value with up to 64 bits of precision.

FAQ

Can mhpmcounter21 be accessed from any privilege level?

No. The CSR table lists mhpmcounter21 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter21 view: S/U-mode reads are controlled by mcounteren.HPM21, and U-mode reads are additionally controlled by scounteren.HPM21. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter21 related to hpmcounter21?

mhpmcounter21 is the machine read/write counter; hpmcounter21 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM21, and U-mode reads are additionally controlled by scounteren.HPM21.