RISC-V mhpmcounter31 CSR Register

Address 0xB1FPrivilege MachineAccess RW / up to 64-bit precisionMachine counters and performance-monitoring CSRs

mhpmcounter31 at 0xB1F is machine hardware performance-monitor counter 31, a WARL counter with up to 64 bits of precision for the platform-defined event selected by mhpmevent31.

Related Search Terms

mhpmcounter31 CSR mhpmcounter31 0xB1F HPM counter 31 mhpmevent31 event machine performance counter up to 64-bit precision

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

COUNT63:0RW

Field Map

Understand mhpmcounter31 By Bit Fields

1 key fields

63:0

COUNT

On RV64 only, reads and writes the complete Machine HPM count for the platform-defined event selected by mhpmevent31; this WARL counter supports up to 64 bits of precision.

COUNT (bits 63:0) — On RV64 only, reads and writes the complete Machine HPM count for the platform-defined event selected by mhpmevent31; this WARL counter supports up to 64 bits of precision.

What This Field Controls

- On RV64 only, reads and writes the complete Machine HPM count for the platform-defined event selected by mhpmevent31; this WARL counter supports up to 64 bits of precision.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmcounter31 is machine HPM counter 31. It does not define event meaning by itself; it counts the platform-defined event currently selected by mhpmevent31 with up to 64 bits of precision.

The official Machine HPM mechanism defines mhpmcounter31 as a WARL counter with up to 64 bits of precision.

mhpmevent31 selects the event; event numbers are platform-defined.

On RV32, mhpmcounter31h provides access to the upper 32 bits.

RISC-V Privileged Architecture Manual: CSR Listing RISC-V Privileged Architecture Manual: Machine-Level ISA

What To Check First When Reading This CSR

- The event source for mhpmcounter31 is determined by mhpmevent31; check the event-selector configuration first.
- S/U-mode reads of the read-only hpmcounter31 shadow are controlled by mcounteren.HPM31; U-mode additionally requires scounteren.HPM31.
- On RV32, mhpmcounter31h accesses bits 63:32 of mhpmcounter31.

Risk Checks Before Writing

- A write to mhpmcounter31 takes effect after the writing instruction has otherwise completed and changes the current count.
- When mcountinhibit.HPM31 is set, the counter does not increment; that bit controls incrementing, not accessibility.

Put It Back Into A Real Flow

Configure mhpmevent31 to select the platform-defined event to count.

Use mcountinhibit.HPM31 when needed to control the counting window.

Read mhpmcounter31 and, on RV32, mhpmcounter31h to obtain the event count with up to 64 bits of precision.

FAQ

Can mhpmcounter31 be accessed from any privilege level?

No. The CSR table lists mhpmcounter31 as a machine read/write CSR. Lower-privilege access is to the corresponding read-only hpmcounter31 view: S/U-mode reads are controlled by mcounteren.HPM31, and U-mode reads are additionally controlled by scounteren.HPM31. A disallowed read raises an illegal-instruction exception.

How is mhpmcounter31 related to hpmcounter31?

mhpmcounter31 is the machine read/write counter; hpmcounter31 is its corresponding lower-privilege read-only shadow. S/U-mode reads are controlled by mcounteren.HPM31, and U-mode reads are additionally controlled by scounteren.HPM31.