Can mhpmevent10h be accessed from any privilege level?
No. The official CSR table lists mhpmevent10h as a Machine-mode MRW CSR; it exists only on RV32 when Sscofpmf is implemented.
CSR Bit Fields
RISC-V mhpmevent10h CSR Register
Address 0x72APrivilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs
mhpmevent10h at 0x72A is the RV32 high-half CSR for bits 63:32 of mhpmevent10, provided with Sscofpmf.
Bit Overview
Hover for details · Click to jumpbit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand mhpmevent10h By Bit Fields
0 key fields
Official Basis & Search Notes
mhpmevent10h is not an independent event selector; it is the RV32 access window for the upper 32 bits of mhpmevent10. It carries Sscofpmf OF and mode-filtering fields.
Sscofpmf standardizes mhpmevent10[63:58] as OF and xINH fields.
mhpmevent10h[31:26] correspond to those standardized upper bits.
The upper event-selector bits remain part of the platform-defined event encoding.
What To Check First When Reading This CSR
- - mhpmevent10h is an RV32-only high-half CSR provided with Sscofpmf.
- - Reading it is equivalent to reading bits 63:32 of mhpmevent10.
- - If Supervisor mode is implemented, the OF bit can also be observed through the corresponding read-only shadow bit in scountovf.
Risk Checks Before Writing
- - Preserve WPRI bits, and do not change EVENT_HI without knowing the platform event encoding.
- - Writing mhpmevent10h changes the upper 32 bits of mhpmevent10, including OF and xINH controls.
Put It Back Into A Real Flow
1
On RV32, read mhpmevent10h to inspect the upper-half state of mhpmevent10.
2
Handle OF or mode-filtering bits as needed.
3
If Supervisor mode is implemented, check overflow state together with mhpmcounter10 readings and scountovf.
FAQ
Should mhpmevent10h and mhpmevent10 be written together?
On RV32, mhpmevent10h reads and writes bits 63:32 of mhpmevent10; accesses to the low-half CSR affect only bits 31:0.