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CSR Bit Fields

RISC-V mhpmevent20h CSR Register

Address 0x734Privilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs

mhpmevent20h at 0x734 is the RV32 high-half CSR for bits 63:32 of mhpmevent20, provided with Sscofpmf.

Related Search Terms
mhpmevent20h CSRmhpmevent20h 0x734mhpmevent20 high halfRV32 high halfSscofpmfOF bitxINH bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand mhpmevent20h By Bit Fields

0 key fields
Official Basis & Search Notes

mhpmevent20h is not an independent event selector; it is the RV32 access window for the upper 32 bits of mhpmevent20. It carries Sscofpmf OF and mode-filtering fields.

Sscofpmf standardizes mhpmevent20[63:58] as OF and xINH fields.
mhpmevent20h[31:26] correspond to those standardized upper bits.
The upper event-selector bits remain part of the platform-defined event encoding.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISARISC-V Sscofpmf Extension

What To Check First When Reading This CSR

  • - mhpmevent20h is an RV32-only high-half CSR provided with Sscofpmf.
  • - Reading it is equivalent to reading bits 63:32 of mhpmevent20.
  • - If Supervisor mode is implemented, the OF bit can also be observed through the corresponding read-only shadow bit in scountovf.

Risk Checks Before Writing

  • - Preserve WPRI bits, and do not change EVENT_HI without knowing the platform event encoding.
  • - Writing mhpmevent20h changes the upper 32 bits of mhpmevent20, including OF and xINH controls.

Put It Back Into A Real Flow

1

On RV32, read mhpmevent20h to inspect the upper-half state of mhpmevent20.

2

Handle OF or mode-filtering bits as needed.

3

Check overflow state together with mhpmcounter20 readings and scountovf.

FAQ

Can mhpmevent20h be accessed from any privilege level?

No. The official CSR table lists mhpmevent20h as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Should mhpmevent20h and mhpmevent20 be written together?

On RV32, handle them as halves of one 64-bit CSR and avoid one path changing the high half while another path changes the low half inconsistently.