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CSR Bit Fields

RISC-V mhpmevent31h CSR Register

Address 0x73FPrivilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs

mhpmevent31h at 0x73F is the RV32 high-half CSR for bits 63:32 of mhpmevent31, provided with Sscofpmf.

Related Search Terms
mhpmevent31h CSRmhpmevent31h 0x73Fmhpmevent31 high halfRV32 high halfSscofpmfOF bitxINH bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:32EVENT_HI23:0WARL
Field Map

Understand mhpmevent31h By Bit Fields

8 key fields
31

OF

RW

Corresponds to mhpmevent31[63], the overflow status and interrupt-disable bit for mhpmcounter31.

OF (bit 31) — Corresponds to mhpmevent31[63], the overflow status and interrupt-disable bit for mhpmcounter31.

What This Field Controls

  • - Corresponds to mhpmevent31[63], the overflow status and interrupt-disable bit for mhpmcounter31.

Common Values

Sscofpmf OF bit
0No overflow recorded

The OF bit for mhpmcounter31 is clear; this bit itself does not disable generation of a later count-overflow interrupt request.

1Overflow recorded

mhpmcounter31 has overflowed and set the sticky OF bit; it remains set until cleared by software and disables new count-overflow interrupt requests for this counter.

30

MINH

RW

Corresponds to mhpmevent31[62]; when set, inhibits M-mode event counting.

MINH (bit 30) — Corresponds to mhpmevent31[62]; when set, inhibits M-mode event counting.

What This Field Controls

  • - Corresponds to mhpmevent31[62]; when set, inhibits M-mode event counting.

Common Values

MINH mode-filter bit
0Counting allowed

mhpmcounter31 event counting in M-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter31 event counting in M-mode is inhibited.

29

SINH

RW

Corresponds to mhpmevent31[61]; when set, inhibits S/HS-mode event counting.

SINH (bit 29) — Corresponds to mhpmevent31[61]; when set, inhibits S/HS-mode event counting.

What This Field Controls

  • - Corresponds to mhpmevent31[61]; when set, inhibits S/HS-mode event counting.

Common Values

SINH mode-filter bit
0Counting allowed

mhpmcounter31 event counting in S/HS-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter31 event counting in S/HS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

28

UINH

RW

Corresponds to mhpmevent31[60]; when set, inhibits U-mode event counting.

UINH (bit 28) — Corresponds to mhpmevent31[60]; when set, inhibits U-mode event counting.

What This Field Controls

  • - Corresponds to mhpmevent31[60]; when set, inhibits U-mode event counting.

Common Values

UINH mode-filter bit
0Counting allowed

mhpmcounter31 event counting in U-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter31 event counting in U-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

27

VSINH

RW

Corresponds to mhpmevent31[59]; when set, inhibits VS-mode event counting.

VSINH (bit 27) — Corresponds to mhpmevent31[59]; when set, inhibits VS-mode event counting.

What This Field Controls

  • - Corresponds to mhpmevent31[59]; when set, inhibits VS-mode event counting.

Common Values

VSINH mode-filter bit
0Counting allowed

mhpmcounter31 event counting in VS-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter31 event counting in VS-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

26

VUINH

RW

Corresponds to mhpmevent31[58]; when set, inhibits VU-mode event counting.

VUINH (bit 26) — Corresponds to mhpmevent31[58]; when set, inhibits VU-mode event counting.

What This Field Controls

  • - Corresponds to mhpmevent31[58]; when set, inhibits VU-mode event counting.

Common Values

VUINH mode-filter bit
0Counting allowed

mhpmcounter31 event counting in VU-mode is not inhibited by this bit; other counter configuration, event selection, and implementation support still apply.

1Counting inhibited

mhpmcounter31 event counting in VU-mode is inhibited; if the associated privilege mode is not implemented, this bit is read-only zero.

25:24

WPRI

WPRI

Corresponds to reserved writes-preserve-values bits mhpmevent31[57:56].

WPRI (bits 25:24) — Corresponds to reserved writes-preserve-values bits mhpmevent31[57:56].

What This Field Controls

  • - Corresponds to reserved writes-preserve-values bits mhpmevent31[57:56].

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

23:0

EVENT_HI

WARL

Corresponds to platform-defined event-selector bits mhpmevent31[55:32].

EVENT_HI (bits 23:0) — Corresponds to platform-defined event-selector bits mhpmevent31[55:32].

What This Field Controls

  • - Corresponds to platform-defined event-selector bits mhpmevent31[55:32].

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mhpmevent31h is not an independent event selector; it is the RV32 access window for the upper 32 bits of mhpmevent31. It carries Sscofpmf OF and mode-filtering fields.

Sscofpmf standardizes mhpmevent31[63:58] as OF and xINH fields.
mhpmevent31h[31:26] correspond to those standardized upper bits.
The upper event-selector bits remain part of the platform-defined event encoding.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISARISC-V Sscofpmf Extension

What To Check First When Reading This CSR

  • - mhpmevent31h is an RV32-only high-half CSR provided with Sscofpmf.
  • - Reading it is equivalent to reading bits 63:32 of mhpmevent31.
  • - The OF bit can also be observed through the corresponding read-only shadow bit in scountovf.

Risk Checks Before Writing

  • - Preserve WPRI bits, and do not change EVENT_HI without knowing the platform event encoding.
  • - Writing mhpmevent31h changes the upper 32 bits of mhpmevent31, including OF and xINH controls.

Put It Back Into A Real Flow

1

On RV32, read mhpmevent31h to inspect the upper-half state of mhpmevent31.

2

Handle OF or mode-filtering bits as needed.

3

Check overflow state together with mhpmcounter31 readings and scountovf.

FAQ

Can mhpmevent31h be accessed from any privilege level?

No. The official CSR table lists mhpmevent31h as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Should mhpmevent31h and mhpmevent31 be written together?

On RV32, handle them as halves of one 64-bit CSR and avoid one path changing the high half while another path changes the low half inconsistently.