RVOPcode
Back To CSR WorkbenchView In Register Browser
CSR Bit Fields

RISC-V mhpmevent31h CSR Register

Address 0x73FPrivilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs

mhpmevent31h at 0x73F is the RV32 high-half CSR for bits 63:32 of mhpmevent31, provided with Sscofpmf.

Related Search Terms
mhpmevent31h CSRmhpmevent31h 0x73Fmhpmevent31 high halfRV32 high halfSscofpmfOF bitxINH bits
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map

Understand mhpmevent31h By Bit Fields

0 key fields
Official Basis & Search Notes

mhpmevent31h is not an independent event selector; it is the RV32 access window for the upper 32 bits of mhpmevent31. It carries Sscofpmf OF and mode-filtering fields.

Sscofpmf standardizes mhpmevent31[63:58] as OF and xINH fields.
mhpmevent31h[31:26] correspond to those standardized upper bits.
The upper event-selector bits remain part of the platform-defined event encoding.
RISC-V Privileged Architecture Manual: CSR ListingRISC-V Privileged Architecture Manual: Machine-Level ISARISC-V Sscofpmf Extension

What To Check First When Reading This CSR

  • - mhpmevent31h is an RV32-only high-half CSR provided with Sscofpmf.
  • - Reading it is equivalent to reading bits 63:32 of mhpmevent31.
  • - If S-mode is implemented, scountovf provides the corresponding read-only OF shadow; reads in S/HS or VS mode remain controlled by mcounteren, or by both mcounteren and hcounteren, respectively.

Risk Checks Before Writing

  • - Preserve WPRI bits, and do not change EVENT_HI without knowing the platform event encoding.
  • - Writing mhpmevent31h changes the upper 32 bits of mhpmevent31, including OF and xINH controls.

Put It Back Into A Real Flow

1

On RV32, read mhpmevent31h to inspect the upper-half state of mhpmevent31.

2

Handle OF or mode-filtering bits as needed.

3

When Supervisor mode is implemented, check overflow state together with mhpmcounter31 readings and scountovf.

FAQ

Can mhpmevent31h be accessed from any privilege level?

No. The official CSR table lists mhpmevent31h as a Machine mode CSR. Lower-privilege software may access the corresponding state only when a relevant standard extension provides an explicit delegation or permission mechanism. Direct CSR access with insufficient privilege, or to an unimplemented CSR, raises an illegal-instruction exception.

Should mhpmevent31h and mhpmevent31 be written together?

On RV32, handle them as halves of one 64-bit CSR and avoid one path changing the high half while another path changes the low half inconsistently.