Can mhpmevent5h be accessed from any privilege level?
No. The official CSR table lists it as a Machine-mode MRW CSR; direct access from a lower privilege level such as S or U raises an illegal-instruction exception.
CSR Bit Fields
RISC-V mhpmevent5h CSR Register
Address 0x725Privilege MachineAccess RW / RV32 high-half / 32-bitMachine counters and performance-monitoring CSRs
mhpmevent5h at 0x725 is the RV32 high-half CSR for bits 63:32 of mhpmevent5, provided with Sscofpmf.
Bit Overview
Hover for details · Click to jumpbit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Field Map
Understand mhpmevent5h By Bit Fields
0 key fields
Official Basis & Search Notes
mhpmevent5h is not an independent event selector; it is the RV32 access window for the upper 32 bits of mhpmevent5. It carries Sscofpmf OF and mode-filtering fields.
Sscofpmf standardizes mhpmevent5[63:58] as OF and xINH fields.
mhpmevent5h[31:26] correspond to those standardized upper bits.
The upper event-selector bits remain part of the platform-defined event encoding.
What To Check First When Reading This CSR
- - mhpmevent5h is an RV32-only high-half CSR provided with Sscofpmf.
- - Reading it is equivalent to reading bits 63:32 of mhpmevent5.
- - When Supervisor mode is implemented, the OF bit can also be observed through the corresponding read-only shadow bit in scountovf.
Risk Checks Before Writing
- - Preserve WPRI bits, and do not change EVENT_HI without knowing the platform event encoding.
- - Writing mhpmevent5h changes the upper 32 bits of mhpmevent5, including OF and xINH controls.
Put It Back Into A Real Flow
1
On RV32, read mhpmevent5h to inspect the upper-half state of mhpmevent5.
2
Handle OF or mode-filtering bits as needed.
3
Check overflow state together with mhpmcounter5 readings and scountovf.
FAQ
Should mhpmevent5h and mhpmevent5 be written together?
On RV32, handle them as halves of one 64-bit CSR and avoid one path changing the high half while another path changes the low half inconsistently.