RISC-V mireg5 CSR Register

Address 0x356Privilege MachineAccess MRW / XLENMachine AIA, timer, and indirect interrupt CSRs

Smcsrind machine indirect register alias CSR; generic select values are extension-defined, but AIA select ranges make mireg5 accesses raise illegal-instruction exceptions.

Related Search Terms

mireg5 CSR mireg5 0x356 Smcsrind indirect CSR mireg alias

Bit Overview

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bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

MIREG_ALIAS63:0MRW

Field Map

Understand mireg5 By Bit Fields

1 key fields

XLEN-1:0

MIREG_ALIAS

MRW

Machine indirect CSR alias window; the actual target and fields are defined by the extension selected by the current miselect value. If miselect is in the AIA ranges 0x30-0x3F or 0x70-0xFF, accessing mireg5 raises an illegal-instruction exception.

MIREG_ALIAS (bits XLEN-1:0) — Machine indirect CSR alias window; the actual target and fields are defined by the extension selected by the current miselect value. If miselect is in the AIA ranges 0x30-0x3F or 0x70-0xFF, accessing mireg5 raises an illegal-instruction exception.

What This Field Controls

- Machine indirect CSR alias window; the actual target and fields are defined by the extension selected by the current miselect value. If miselect is in the AIA ranges 0x30-0x3F or 0x70-0xFF, accessing mireg5 raises an illegal-instruction exception.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

Smcsrind machine indirect register alias CSR; generic select values are extension-defined, but AIA select ranges make mireg5 accesses raise illegal-instruction exceptions.

The official Smcsrind table lists mireg5 at 0x356, with MRW access and XLEN width.

mireg* CSR numbers are not consecutive because 0x354 is miph.

AIA specifies that when miselect is in 0x30-0x3F or 0x70-0xFF, accessing mireg5 raises an illegal-instruction exception.

Access through mireg* with an unimplemented select value is not portable behavior.

RISC-V Privileged Architecture: Smcsrind/Sscsrind Indirect CSR Access RISC-V Privileged Architecture: CSR Listing RISC-V Advanced Interrupt Architecture: Machine-level CSRs and indirect interrupt-file registers

What To Check First When Reading This CSR

- Confirm Smcsrind or the AIA indirect CSR mechanism before accessing mireg5.
- AIA select ranges 0x30-0x3F and 0x70-0xFF use mireg only; accessing mireg5 in those ranges raises an illegal-instruction exception.
- mireg* access with an unimplemented select value is UNSPECIFIED and must not be used as a portable software assumption.

Risk Checks Before Writing

- Write miselect before accessing mireg*; do not confuse CSR numbers with select values.
- If miselect selects an AIA priority or IMSIC external-interrupt range, do not write mireg5; AIA accesses those ranges through mireg.
- The effect of writing mireg* depends entirely on the current select value and the allocating extension.

Put It Back Into A Real Flow

Confirm Smcsrind/AIA indirect access support.

Write or read miselect to select the target.

If the select value is in the AIA ranges 0x30-0x3F or 0x70-0xFF, use mireg rather than mireg5.

Otherwise access the target through the appropriate mireg* window and interpret the result by the extension that allocated the select value.

FAQ

Does mireg5 directly represent one fixed register?

No. mireg* is an alias window; the actual target is determined by the current miselect value and allocating extension. AIA ranges 0x30-0x3F and 0x70-0xFF are accessed through mireg only, so mireg5 raises an illegal-instruction exception in those ranges.

What happens for an unimplemented select value?

The official spec defines this M-mode access as UNSPECIFIED and notes implementations are typically expected to raise an illegal-instruction exception.