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CSR Bit Fields

RISC-V miselect CSR Register

Address 0x350Privilege MachineAccess MRW / XLENMachine AIA, timer, and indirect interrupt CSRs

Smcsrind machine indirect register select CSR; selects the target reached by subsequent mireg* accesses.

Related Search Terms
miselect CSRmiselect 0x350Smcsrindindirect CSRCSR selector
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
MISELECT63:0MRW
Field Map

Understand miselect By Bit Fields

1 key fields
XLEN-1:0

MISELECT

MRW

Machine indirect CSR select value; standard, reserved, and custom values follow Smcsrind rules.

MISELECT (bits XLEN-1:0) — Machine indirect CSR select value; standard, reserved, and custom values follow Smcsrind rules.

What This Field Controls

  • - Machine indirect CSR select value; standard, reserved, and custom values follow Smcsrind rules.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

Smcsrind machine indirect register select CSR; selects the target reached by subsequent mireg* accesses.

The official Smcsrind table lists miselect at 0x350, with MRW access and XLEN width.
miselect determines the register state actually accessed by mireg*.
Access through mireg* with an unimplemented select value is not portable behavior.
RISC-V Privileged Architecture: Smcsrind/Sscsrind Indirect CSR AccessRISC-V Privileged Architecture: CSR Listing

What To Check First When Reading This CSR

  • - Confirm Smcsrind or the AIA indirect CSR mechanism before accessing miselect.
  • - miselect is WARL and may implement only enough bits for implemented select values; it may be read-only zero if no extension uses it.

Risk Checks Before Writing

  • - Write miselect before accessing mireg*; do not confuse CSR numbers with select values.
  • - The effect of writing mireg* depends entirely on the current select value and the allocating extension.

Put It Back Into A Real Flow

1

Confirm Smcsrind/AIA indirect access support.

2

Write or read miselect to select the target.

3

Access the target through the appropriate mireg* window and interpret the result by the extension that allocated the select value.

FAQ

Does miselect directly represent one fixed register?

No. miselect holds the select value; data is accessed through the mireg* windows.

What happens for an unimplemented select value?

The official spec defines this M-mode access as UNSPECIFIED and notes implementations are typically expected to raise an illegal-instruction exception.