RISC-V mncause CSR Register

Address 0x742Privilege MachineAccess RW / MXLENMachine RNMI CSRs

Smrnmi's MXLEN-bit RNMI cause CSR.

Related Search Terms

mncause CSR mncause 0x742 Smrnmi RNMI cause

Bit Overview

Hover for details · Click to jump

bit 3 = only bit 3; bits 12..11 = bits 12 down to 11

MSBLSB

Interrupt63Hardware-updated Exception Code62:0WARL

Field Map

Understand mncause By Bit Fields

2 key fields

XLEN-1

Interrupt

Hardware-updated

Is 1 for an interrupt RNMI and 0 for an M-mode exception that resulted in an Smdbltrp double trap.

Interrupt (bits XLEN-1) — Is 1 for an interrupt RNMI and 0 for an M-mode exception that resulted in an Smdbltrp double trap.

What This Field Controls

- Is 1 for an interrupt RNMI and 0 for an M-mode exception that resulted in an Smdbltrp double trap.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

XLEN-2:0

Exception Code

WARL

For an interrupt, holds the RNMI cause or zero when RNMI causes are unsupported; for a double trap, holds the precipitating exception code.

Exception Code (bits XLEN-2:0) — For an interrupt, holds the RNMI cause or zero when RNMI causes are unsupported; for a double trap, holds the precipitating exception code.

What This Field Controls

- For an interrupt, holds the RNMI cause or zero when RNMI causes are unsupported; for a double trap, holds the precipitating exception code.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

Smrnmi's MXLEN-bit RNMI cause CSR.

The top bit distinguishes an interrupt from a double-trap exception; lower bits hold the corresponding cause.

RISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

- mncause is defined only by Smrnmi and is absent otherwise.
- For an interrupt RNMI whose cause is unsupported, Interrupt is 1 and hardware writes zero to the low bits.

Risk Checks Before Writing

- Treat this CSR as architectural state written on RNMI entry; legal cause values depend on implemented RNMI causes.

Put It Back Into A Real Flow

Confirm Smrnmi is implemented.

Read the top bit and cause field in the RNMI handler.