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CSR Bit Fields

RISC-V mncause CSR Register

Address 0x742Privilege MachineAccess RW / MXLEN/XLENReserved, custom, or uncategorized CSRs

RNMI cause register recording the RNMI interrupt or double-trap exception cause code.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Interrupt63RWCODE62:0RW
Field Map

Understand mncause By Bit Fields

2 key fields
XLEN-1

Interrupt

RW

Set for an interrupt RNMI cause; clear for an M-mode exception that resulted in a double trap.

Interrupt (bits XLEN-1) — Set for an interrupt RNMI cause; clear for an M-mode exception that resulted in a double trap.

What This Field Controls

  • - Set for an interrupt RNMI cause; clear for an M-mode exception that resulted in a double trap.

Common Values

mncause.Interrupt
0Exception / double trap

mncause records the M-mode exception cause that precipitated a double trap.

1RNMI interrupt

mncause records an RNMI interrupt cause.

XLEN-2:0

CODE

RW

RNMI cause code or the exception cause code that precipitated a double trap.

CODE (bits XLEN-2:0) — RNMI cause code or the exception cause code that precipitated a double trap.

What This Field Controls

  • - RNMI cause code or the exception cause code that precipitated a double trap.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mncause; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x742 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mncause to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.