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CSR Bit Fields

RISC-V mnepc CSR Register

Address 0x741Privilege MachineAccess MRW (WARL, Smrnmi) / MXLENReserved, custom, or uncategorized CSRs

An Smrnmi Machine-mode WARL RNMI program counter that holds the interrupted instruction's PC on RNMI-handler entry.

Related Search Terms
mnepc CSRmnepc Smrnmimnepc IALIGNRNMI return PC
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
VALUE63:0RW (WARL)
Field Map

Understand mnepc By Bit Fields

1 key fields
MXLEN-1:0

VALUE

RW (WARL)

The MXLEN-bit RNMI return PC. Bit 0 is always zero; on an implementation supporting only IALIGN=32, bits 1:0 are always zero; where IALIGN can change, bit 1 is masked to zero on reads and MNRET's implicit read while IALIGN=32, but remains writable. Before a write, an implementation may convert an invalid address to another invalid address it can hold.

VALUE (bits MXLEN-1:0) — The MXLEN-bit RNMI return PC. Bit 0 is always zero; on an implementation supporting only IALIGN=32, bits 1:0 are always zero; where IALIGN can change, bit 1 is masked to zero on reads and MNRET's implicit read while IALIGN=32, but remains writable. Before a write, an implementation may convert an invalid address to another invalid address it can hold.

What This Field Controls

  • - The MXLEN-bit RNMI return PC. Bit 0 is always zero; on an implementation supporting only IALIGN=32, bits 1:0 are always zero; where IALIGN can change, bit 1 is masked to zero on reads and MNRET's implicit read while IALIGN=32, but remains writable. Before a write, an implementation may convert an invalid address to another invalid address it can hold.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

mnepc is Smrnmi's WARL RNMI return PC; MNRET uses it to restore the program counter.

Section 8.3 requires it to hold every valid virtual address.
Bit 0 is always zero, while bit 1's read mask and writability depend on the IALIGN implementation.
RISC-V Privileged Architecture Manual, Sections 8.3-8.5

What To Check First When Reading This CSR

  • - mnepc is added only by Smrnmi and listed as MRW; the complete register is WARL.
  • - On RNMI-handler entry it holds the PC of the interrupted instruction, and MNRET reads it implicitly.
  • - Its low-bit behavior depends on IALIGN: when IALIGN=32 on an implementation that can change IALIGN, mnepc[1] reads as zero but remains writable.

Risk Checks Before Writing

  • - mnepc must hold all valid virtual addresses but need not hold all invalid addresses; before a write an implementation may convert an invalid address to another invalid address it can hold.
  • - Do not interpret bit 1's read mask while IALIGN=32 as making it unwritable.

Put It Back Into A Real Flow

1

Confirm that the hart implements Smrnmi.

2

RNMI entry writes the interrupted instruction's PC to mnepc.

3

MNRET implicitly reads mnepc to restore the PC.

FAQ

Is mnepc[1] unwritable when IALIGN=32?

No. On an implementation with switchable IALIGN, it is read-masked to zero while IALIGN=32 but remains writable.