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CSR Bit Fields

RISC-V mnstatus CSR Register

Address 0x744Privilege MachineAccess RW / MXLEN/XLENReserved, custom, or uncategorized CSRs

RNMI status register saving interrupted-context privilege, virtualization, and RNMI enable state.

Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:13Reserved2:0
Field Map

Understand mnstatus By Bit Fields

4 key fields
12:11

MNPP

WARL-H

Previous privilege mode of the interrupted context on RNMI entry, encoded like mstatus.MPP.

MNPP (bits 12:11) — Previous privilege mode of the interrupted context on RNMI entry, encoded like mstatus.MPP.

What This Field Controls

  • - Previous privilege mode of the interrupted context on RNMI entry, encoded like mstatus.MPP.

Common Values

mnstatus.MNPP
0User

The interrupted context previous privilege mode on RNMI entry was User.

1Supervisor

The interrupted context previous privilege mode on RNMI entry was Supervisor.

2Reserved

Reserved encoding; portable software must not write or depend on it.

3Machine

The interrupted context previous privilege mode on RNMI entry was Machine.

9

MNPELP

RW-H

If Zicfilp is implemented, holds the pre-RNMI ELP state; otherwise reserved.

MNPELP (bit 9) — If Zicfilp is implemented, holds the pre-RNMI ELP state; otherwise reserved.

What This Field Controls

  • - If Zicfilp is implemented, holds the pre-RNMI ELP state; otherwise reserved.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7

MNPV

WARL-H

Virtualization mode of the interrupted context on RNMI entry, encoded like mstatus.MPV.

MNPV (bit 7) — Virtualization mode of the interrupted context on RNMI entry, encoded like mstatus.MPV.

What This Field Controls

  • - Virtualization mode of the interrupted context on RNMI entry, encoded like mstatus.MPV.

Common Values

mnstatus.MNPV
0Not virtualized

The interrupted context on RNMI entry was not in a virtualized guest mode.

1Virtualized

The interrupted context on RNMI entry was in a virtualized guest mode.

3

NMIE

RW-H/RW1S

RNMI global enable bit; reset to 0, software can set it, attempts to clear it have no effect, RNMI entry clears it, and MNRET sets it.

NMIE (bit 3) — RNMI global enable bit; reset to 0, software can set it, attempts to clear it have no effect, RNMI entry clears it, and MNRET sets it.

What This Field Controls

  • - RNMI global enable bit; reset to 0, software can set it, attempts to clear it have no effect, RNMI entry clears it, and MNRET sets it.

Common Values

mnstatus.NMIE
0RNMI disabled

RNMI global enable is clear; RNMI entry clears this bit in hardware. Software attempts to clear it have no effect.

1RNMI enabled

RNMI global enable is set; software can set it, and MNRET also sets it.

What To Check First When Reading This CSR

  • - First confirm that the current hart implements mnstatus; unimplemented or insufficiently privileged accesses raise an illegal-instruction exception.
  • - Use address 0x744 and the lowest access privilege (Machine) to decide whether software may read it directly.
  • - Do not assume fixed values for reserved, WARL, or WLRL bits; interpret the value according to the specification and implementation.

Risk Checks Before Writing

  • - Preserve bits that are not being changed so reserved or implementation-defined fields are not written with invalid values.
  • - Prefer CSRRS/CSRRC for local set/clear operations to avoid CSRRW overwriting concurrently updated status bits.

Put It Back Into A Real Flow

1

During initialization or the relevant privileged flow, software reads mnstatus to observe the current state.

2

Modify only the target fields while preserving all other bits.

3

Read back the CSR or validate through later trap, interrupt, or context-switch behavior that the setting took effect.