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CSR Bit Fields

RISC-V mnstatus CSR Register

Address 0x744Privilege MachineAccess RW / MXLENMachine RNMI CSRs

Smrnmi's MXLEN-bit RNMI status CSR, holding interrupted-context state and NMIE.

Related Search Terms
mnstatus CSRmnstatus 0x744NMIEMNPPSmrnmi
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
Reserved63:13RO0Reserved2:0RO0
Field Map

Understand mnstatus By Bit Fields

9 key fields
XLEN-1:13

Reserved

RO0

Reserved; software writes zero and hardware returns zero.

Reserved (bits XLEN-1:13) — Reserved; software writes zero and hardware returns zero.

What This Field Controls

  • - Reserved; software writes zero and hardware returns zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

12:11

MNPP

WARL/hardware-updated

Previous privilege mode saved on RNMI entry, encoded like mstatus.MPP.

MNPP (bits 12:11) — Previous privilege mode saved on RNMI entry, encoded like mstatus.MPP.

What This Field Controls

  • - Previous privilege mode saved on RNMI entry, encoded like mstatus.MPP.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

10

Reserved

RO0

Reserved and reads zero.

Reserved (bit 10) — Reserved and reads zero.

What This Field Controls

  • - Reserved and reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

9

MNPELP

Hardware-updated (Zicfilp)

Only with Zicfilp, saves prior ELP; RNMI entry sets it to ELP and clears ELP.

MNPELP (bit 9) — Only with Zicfilp, saves prior ELP; RNMI entry sets it to ELP and clears ELP.

What This Field Controls

  • - Only with Zicfilp, saves prior ELP; RNMI entry sets it to ELP and clears ELP.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

8

Reserved

RO0

Reserved and reads zero.

Reserved (bit 8) — Reserved and reads zero.

What This Field Controls

  • - Reserved and reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

7

MNPV

WARL/hardware-updated

Virtualization mode saved on RNMI entry, encoded like mstatus.MPV.

MNPV (bit 7) — Virtualization mode saved on RNMI entry, encoded like mstatus.MPV.

What This Field Controls

  • - Virtualization mode saved on RNMI entry, encoded like mstatus.MPV.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

6:4

Reserved

RO0

Reserved and reads zero.

Reserved (bits 6:4) — Reserved and reads zero.

What This Field Controls

  • - Reserved and reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

3

NMIE

Settable/hardware-updated

Resets to 0; software may set it but clearing has no effect; RNMI entry clears it and MNRET sets it.

NMIE (bit 3) — Resets to 0; software may set it but clearing has no effect; RNMI entry clears it and MNRET sets it.

What This Field Controls

  • - Resets to 0; software may set it but clearing has no effect; RNMI entry clears it and MNRET sets it.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

2:0

Reserved

RO0

Reserved and reads zero.

Reserved (bits 2:0) — Reserved and reads zero.

What This Field Controls

  • - Reserved and reads zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

Official Basis & Search Notes

Smrnmi's MXLEN-bit RNMI status CSR, holding interrupted-context state and NMIE.

RNMI entry saves privilege, virtualization, and optional ELP state; MNRET uses them to resume execution.
RISC-V Privileged Architecture Manual

What To Check First When Reading This CSR

  • - mnstatus exists only with Smrnmi.
  • - When NMIE=0, the hart behaves as if mstatus.MPRV were clear.

Risk Checks Before Writing

  • - Do not attempt to clear NMIE by writing zero; that has no effect.
  • - Reserved bits must be written zero.

Put It Back Into A Real Flow

1

Confirm Smrnmi is implemented.

2

Let RNMI entry save state and use MNRET to resume.