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CSR Bit Fields

RISC-V pmpcfg10 CSR Register

Address 0x3AAPrivilege MachineAccess RW / MXLEN: 32 bits on RV32; 64 bits on RV64Machine physical memory protection CSRs

pmpcfg10 (0x3AA) is a machine PMP configuration CSR packing pmp40cfg-pmp43cfg on RV32 and pmp40cfg-pmp47cfg on RV64.

Related Search Terms
pmpcfg10 CSRpmpcfg10 0x3AAPMP R W XPMP A fieldPMP L bitPMP entries 40-47
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
pmp47cfg.L63WARL/may be RO0pmp40cfg.R0Collective WARL (R/W/X)
Field Map

Understand pmpcfg10 By Bit Fields

48 key fields
7

pmp40cfg.L

WARL/may be RO0

Lock bit for PMP entry 40. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp40cfg.L (bit 7) — Lock bit for PMP entry 40. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 40. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp40cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
6:5

pmp40cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp40cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp40cfg.reserved (bits 6:5) — Bits 6:5 of pmp40cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp40cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
4:3

pmp40cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 40. This field is WARL and may be implemented as read-only zero.

pmp40cfg.A (bits 4:3) — Address-matching mode for PMP entry 40. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 40. This field is WARL and may be implemented as read-only zero.

Common Values

pmp40cfg.A
0OFF

PMP entry 40 is disabled and matches no addresses.

1TOR

PMP entry 40 uses top-of-range matching; the upper bound comes from pmpaddr40, and the lower bound comes from pmpaddr39.

2NA4

PMP entry 40 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 40 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr40.

↗Open Official Manual
2

pmp40cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp40cfg.X (bit 2) — X bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp40cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
1

pmp40cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp40cfg.W (bit 1) — W bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp40cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
0

pmp40cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp40cfg.R (bit 0) — R bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 40; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp40cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
15

pmp41cfg.L

WARL/may be RO0

Lock bit for PMP entry 41. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp41cfg.L (bit 15) — Lock bit for PMP entry 41. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 41. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp41cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
14:13

pmp41cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp41cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp41cfg.reserved (bits 14:13) — Bits 6:5 of pmp41cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp41cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
12:11

pmp41cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 41. This field is WARL and may be implemented as read-only zero.

pmp41cfg.A (bits 12:11) — Address-matching mode for PMP entry 41. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 41. This field is WARL and may be implemented as read-only zero.

Common Values

pmp41cfg.A
0OFF

PMP entry 41 is disabled and matches no addresses.

1TOR

PMP entry 41 uses top-of-range matching; the upper bound comes from pmpaddr41, and the lower bound comes from pmpaddr40.

2NA4

PMP entry 41 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 41 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr41.

↗Open Official Manual
10

pmp41cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp41cfg.X (bit 10) — X bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp41cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
9

pmp41cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp41cfg.W (bit 9) — W bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp41cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
8

pmp41cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp41cfg.R (bit 8) — R bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 41; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp41cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
23

pmp42cfg.L

WARL/may be RO0

Lock bit for PMP entry 42. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp42cfg.L (bit 23) — Lock bit for PMP entry 42. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 42. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp42cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
22:21

pmp42cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp42cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp42cfg.reserved (bits 22:21) — Bits 6:5 of pmp42cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp42cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
20:19

pmp42cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 42. This field is WARL and may be implemented as read-only zero.

pmp42cfg.A (bits 20:19) — Address-matching mode for PMP entry 42. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 42. This field is WARL and may be implemented as read-only zero.

Common Values

pmp42cfg.A
0OFF

PMP entry 42 is disabled and matches no addresses.

1TOR

PMP entry 42 uses top-of-range matching; the upper bound comes from pmpaddr42, and the lower bound comes from pmpaddr41.

2NA4

PMP entry 42 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 42 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr42.

↗Open Official Manual
18

pmp42cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp42cfg.X (bit 18) — X bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp42cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
17

pmp42cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp42cfg.W (bit 17) — W bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp42cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
16

pmp42cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp42cfg.R (bit 16) — R bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 42; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp42cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
31

pmp43cfg.L

WARL/may be RO0

Lock bit for PMP entry 43. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp43cfg.L (bit 31) — Lock bit for PMP entry 43. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 43. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp43cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
30:29

pmp43cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp43cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp43cfg.reserved (bits 30:29) — Bits 6:5 of pmp43cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp43cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
28:27

pmp43cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 43. This field is WARL and may be implemented as read-only zero.

pmp43cfg.A (bits 28:27) — Address-matching mode for PMP entry 43. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 43. This field is WARL and may be implemented as read-only zero.

Common Values

pmp43cfg.A
0OFF

PMP entry 43 is disabled and matches no addresses.

1TOR

PMP entry 43 uses top-of-range matching; the upper bound comes from pmpaddr43, and the lower bound comes from pmpaddr42.

2NA4

PMP entry 43 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 43 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr43.

↗Open Official Manual
26

pmp43cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp43cfg.X (bit 26) — X bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp43cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
25

pmp43cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp43cfg.W (bit 25) — W bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp43cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
24

pmp43cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp43cfg.R (bit 24) — R bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 43; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp43cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
39

pmp44cfg.L

WARL/may be RO0

Lock bit for PMP entry 44. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp44cfg.L (bit 39) — Lock bit for PMP entry 44. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 44. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp44cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
38:37

pmp44cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp44cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp44cfg.reserved (bits 38:37) — Bits 6:5 of pmp44cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp44cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
36:35

pmp44cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 44. This field is WARL and may be implemented as read-only zero.

pmp44cfg.A (bits 36:35) — Address-matching mode for PMP entry 44. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 44. This field is WARL and may be implemented as read-only zero.

Common Values

pmp44cfg.A
0OFF

PMP entry 44 is disabled and matches no addresses.

1TOR

PMP entry 44 uses top-of-range matching; the upper bound comes from pmpaddr44, and the lower bound comes from pmpaddr43.

2NA4

PMP entry 44 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 44 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr44.

↗Open Official Manual
34

pmp44cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp44cfg.X (bit 34) — X bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp44cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
33

pmp44cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp44cfg.W (bit 33) — W bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp44cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
32

pmp44cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp44cfg.R (bit 32) — R bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 44; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp44cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
47

pmp45cfg.L

WARL/may be RO0

Lock bit for PMP entry 45. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp45cfg.L (bit 47) — Lock bit for PMP entry 45. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 45. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp45cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
46:45

pmp45cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp45cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp45cfg.reserved (bits 46:45) — Bits 6:5 of pmp45cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp45cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
44:43

pmp45cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 45. This field is WARL and may be implemented as read-only zero.

pmp45cfg.A (bits 44:43) — Address-matching mode for PMP entry 45. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 45. This field is WARL and may be implemented as read-only zero.

Common Values

pmp45cfg.A
0OFF

PMP entry 45 is disabled and matches no addresses.

1TOR

PMP entry 45 uses top-of-range matching; the upper bound comes from pmpaddr45, and the lower bound comes from pmpaddr44.

2NA4

PMP entry 45 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 45 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr45.

↗Open Official Manual
42

pmp45cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp45cfg.X (bit 42) — X bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp45cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
41

pmp45cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp45cfg.W (bit 41) — W bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp45cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
40

pmp45cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp45cfg.R (bit 40) — R bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 45; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp45cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
55

pmp46cfg.L

WARL/may be RO0

Lock bit for PMP entry 46. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp46cfg.L (bit 55) — Lock bit for PMP entry 46. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 46. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp46cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
54:53

pmp46cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp46cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp46cfg.reserved (bits 54:53) — Bits 6:5 of pmp46cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp46cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
52:51

pmp46cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 46. This field is WARL and may be implemented as read-only zero.

pmp46cfg.A (bits 52:51) — Address-matching mode for PMP entry 46. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 46. This field is WARL and may be implemented as read-only zero.

Common Values

pmp46cfg.A
0OFF

PMP entry 46 is disabled and matches no addresses.

1TOR

PMP entry 46 uses top-of-range matching; the upper bound comes from pmpaddr46, and the lower bound comes from pmpaddr45.

2NA4

PMP entry 46 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 46 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr46.

↗Open Official Manual
50

pmp46cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp46cfg.X (bit 50) — X bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp46cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
49

pmp46cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp46cfg.W (bit 49) — W bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp46cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
48

pmp46cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp46cfg.R (bit 48) — R bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 46; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp46cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
63

pmp47cfg.L

WARL/may be RO0

Lock bit for PMP entry 47. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

pmp47cfg.L (bit 63) — Lock bit for PMP entry 47. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

What This Field Controls

  • - Lock bit for PMP entry 47. This field is WARL and may be implemented as read-only zero; Smepmp RLB/MML alters locking or permission interpretation.

Common Values

pmp47cfg.L
0L=0

In base PMP, the entry is unlocked and matching M-mode accesses bypass R/W/X, although pmpaddrN may still be locked by a following locked TOR entry. Smepmp MML can change the permission interpretation.

1L=1

In base PMP, locks the entry: writes to pmpNcfg/pmpaddrN are ignored until hart reset, TOR also locks the preceding pmpaddr, and R/W/X apply to all privilege modes. Smepmp RLB/MML rules can change this interpretation.

↗Open Official Manual
62:61

pmp47cfg.reserved

WARL/may be RO0

Bits 6:5 of pmp47cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

pmp47cfg.reserved (bits 62:61) — Bits 6:5 of pmp47cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

What This Field Controls

  • - Bits 6:5 of pmp47cfg are reserved zero in the standard PMP layout; as PMP CSR fields they are WARL and may be implemented as read-only zero.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
60:59

pmp47cfg.A

WARL/may be RO0

Address-matching mode for PMP entry 47. This field is WARL and may be implemented as read-only zero.

pmp47cfg.A (bits 60:59) — Address-matching mode for PMP entry 47. This field is WARL and may be implemented as read-only zero.

What This Field Controls

  • - Address-matching mode for PMP entry 47. This field is WARL and may be implemented as read-only zero.

Common Values

pmp47cfg.A
0OFF

PMP entry 47 is disabled and matches no addresses.

1TOR

PMP entry 47 uses top-of-range matching; the upper bound comes from pmpaddr47, and the lower bound comes from pmpaddr46.

2NA4

PMP entry 47 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

3NAPOT

PMP entry 47 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr47.

↗Open Official Manual
58

pmp47cfg.X

Collective WARL (R/W/X)

X bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp47cfg.X (bit 58) — X bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - X bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp47cfg.X
0X=0

When mseccfg.MML=0, this does not grant execute permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1X=1

When mseccfg.MML=0, this permits instruction fetches for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
57

pmp47cfg.W

Collective WARL (R/W/X)

W bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp47cfg.W (bit 57) — W bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - W bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp47cfg.W
0W=0

When mseccfg.MML=0, this does not grant write permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1W=1

When mseccfg.MML=0, this permits writes for a matching entry when R=1; R=0, W=1 is reserved in base PMP; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
56

pmp47cfg.R

Collective WARL (R/W/X)

R bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

pmp47cfg.R (bit 56) — R bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

What This Field Controls

  • - R bit for PMP entry 47; R/W/X form a collective WARL field. The per-bit values below describe base PMP (mseccfg.MML=0); with MML=1, use the collective Smepmp L/R/W/X encoding.

Common Values

pmp47cfg.R
0R=0

When mseccfg.MML=0, this does not grant read permission; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

1R=1

When mseccfg.MML=0, this permits reads for a matching entry; M-mode is constrained by the permission only when L=1. With MML=1, this bit cannot be interpreted in isolation.

↗Open Official Manual
Official Basis & Search Notes

pmpcfg10 packs four 8-bit PMP configurations on RV32 and eight on RV64; each contains L, A, X, W, R, and two reserved zero bits.

The Machine ISA Physical Memory Protection CSRs subsection defines the address, MXLEN packing, M-mode-only access, and WARL/RO0 behavior.
A encodes OFF, TOR, NA4, or NAPOT; platform grain may make NA4 unselectable.
Base PMP and Smepmp with MML=1 interpret L/R/W/X differently, so field values must be read with mseccfg state.
RISC-V ISA Manual 2026-07-09 release - Machine ISA PMPRISC-V Privileged Architecture - Physical Memory ProtectionRISC-V Privileged Architecture - Smepmp Physical Memory Protection Rules

What To Check First When Reading This CSR

  • - pmpcfg10 contains entries 40-43 on RV32 and entries 40-47 in the same CSR on RV64.
  • - PMP is optional; implementations may provide 0, 16, or 64 entries, and every PMP CSR field is WARL and may be read-only zero.
  • - PMP CSRs are accessible only to M-mode.
  • - The M-mode permission bypass described on this page applies only when effective privilege is M; mstatus.MPRV can make an M-mode data access undergo PMP checks with effective S/U privilege.
  • - At reset, writable PMP A and L fields become 0 unless the platform mandates different values for some PMP registers; other PMP field reset values are unspecified, but no WARL field contains an illegal value.

Risk Checks Before Writing

  • - R/W/X form one collective WARL field. In base PMP (mseccfg.MML=0), combinations with R=0 and W=1 are reserved; Smepmp collectively reinterprets L/R/W/X when MML=1.
  • - L=1 locks pmpNcfg and pmpaddrN until hart reset; with A=TOR it also locks the preceding pmpaddr. Smepmp mseccfg.RLB can bypass locking rules.
  • - Read back WARL fields after writing; do not assume an unimplemented permission or matching mode is accepted.

Put It Back Into A Real Flow

1

Choose OFF, TOR, NA4, or NAPOT in A and encode the range in pmpaddrN (and the preceding address register for TOR).

2

Interpret and write the collective WARL L/R/W/X encoding according to the current mseccfg.MML state.

3

Read back pmpcfg and pmpaddr to confirm the implemented WARL values; set L only after finalizing the configuration.

FAQ

Does pmpcfg10 contain the same number of entries on RV32 and RV64?

No. RV32 pmpcfg10 packs pmp40cfg-pmp43cfg, while RV64 pmpcfg10 packs pmp40cfg-pmp47cfg.