RISC-V pmpcfg11 CSR Register

PMP entry 44 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr44 may still be locked by a later locked TOR entry.

PMP entry 44 is locked; writes to pmp44cfg and pmpaddr44 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr43 is also locked.

PMP entry 44 is disabled and matches no addresses.

PMP entry 44 uses top-of-range matching; the upper bound comes from pmpaddr44, and the lower bound comes from pmpaddr43.

PMP entry 44 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 44 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr44.

PMP entry 44 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 44 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 44 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 44 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 44 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 44 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 45 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr45 may still be locked by a later locked TOR entry.

PMP entry 45 is locked; writes to pmp45cfg and pmpaddr45 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr44 is also locked.

PMP entry 45 is disabled and matches no addresses.

PMP entry 45 uses top-of-range matching; the upper bound comes from pmpaddr45, and the lower bound comes from pmpaddr44.

PMP entry 45 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 45 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr45.

PMP entry 45 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 45 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 45 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 45 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 45 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 45 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 46 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr46 may still be locked by a later locked TOR entry.

PMP entry 46 is locked; writes to pmp46cfg and pmpaddr46 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr45 is also locked.

PMP entry 46 is disabled and matches no addresses.

PMP entry 46 uses top-of-range matching; the upper bound comes from pmpaddr46, and the lower bound comes from pmpaddr45.

PMP entry 46 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 46 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr46.

PMP entry 46 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 46 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 46 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 46 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 46 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 46 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 47 is not locked; this entry's configuration may be modified under WARL rules. M-mode accesses matching this entry succeed, and R/W/X permissions constrain only S/U effective-privilege accesses. Note that pmpaddr47 may still be locked by a later locked TOR entry.

PMP entry 47 is locked; writes to pmp47cfg and pmpaddr47 are ignored until hart reset, and R/W/X permissions apply to all privilege modes. If A=TOR, pmpaddr46 is also locked.

PMP entry 47 is disabled and matches no addresses.

PMP entry 47 uses top-of-range matching; the upper bound comes from pmpaddr47, and the lower bound comes from pmpaddr46.

PMP entry 47 matches a naturally aligned four-byte region; if the platform PMP grain does not support NA4, this encoding is not selectable.

PMP entry 47 matches a naturally aligned power-of-two region of at least 8 bytes, with the size encoded in low-order bits of pmpaddr47.

PMP entry 47 does not grant execute permission; matching S/U instruction fetches fail, while M-mode instruction fetches are constrained by this bit only when this entry is locked.

PMP entry 47 grants execute permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.

PMP entry 47 does not grant write permission; matching S/U store, AMO, and other write-class accesses fail, while M-mode writes are constrained by this bit only when this entry is locked.

PMP entry 47 grants write permission only when R=1; the R=0 and W=1 combination is officially reserved and is not a portable configuration.

PMP entry 47 does not grant read permission; matching S/U read accesses fail, while M-mode reads are constrained by this bit only when this entry is locked.

PMP entry 47 grants read permission when this entry matches and other PMP, PMA, and privilege rules also allow the access.